component
LMUN5316DW1T1G
Public Made by Adomby adom
LRC Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownLMUN5316DW1T1G
LRC · Digital Transistors · SOT-363
LMUN5316DW1T1G from LRC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EMITTER 2 | passive | Emitter of transistor Q2 (NPN); the device maximum ratings are 50 Vdc collector-emitter and 100 mAdc collector current, common to both transistors. |
| 2 | BASE 2 | input | Base of transistor Q2, driven through the integrated series base resistor R1, which the datasheet gives as 4.7 k for the LMUN5316DW1T1G. |
| 3 | COLLECTOR 1 | passive | Collector of transistor Q1 (PNP, per the note on page 3); rated for 50 Vdc collector-base and collector-emitter voltage and 100 mAdc collector current maximum. |
| 4 | EMITTER 1 | passive | Emitter of transistor Q1 (PNP), the return of the integrated bias network for that transistor. |
| 5 | BASE 1 | input | Base of transistor Q1 (PNP), driven through the integrated series base resistor R1 of the monolithic bias network. |
| 6 | COLLECTOR 2 | passive | Collector of transistor Q2 (NPN); rated for 50 Vdc collector-base and collector-emitter voltage and 100 mAdc collector current maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input resistor R1 | R1 | 3.3 | 4.7 | 6.1 | k | 3 | |
| DC Current Gain | hFE | 160 | 350 | VCE = 10 V, IC = 5.0 mA | 3 | ||
| Collector-Emitter Saturation Voltage | VCE(sat) | 0.25 | Vdc | IC = 10 mA, IB = 1 mA | 3 | ||
| Output Voltage (on) | VOL | 0.2 | Vdc | VCC = 5.0 V, VB = 2.5 V, RL = 1.0 k | 3 | ||
| Output Voltage (off) | VOH | 4.9 | Vdc | VCC = 5.0 V, VB = 0.25 V, RL = 1.0 k | 3 | ||
| Collector-Base Cutoff Current | ICBO | 100 | nAdc | VCB = 50 V, IE = 0 | 4 | ||
| Collector-Emitter Cutoff Current | ICEO | 500 | nAdc | VCE = 50 V, IB = 0 | 4 | ||
| Emitter-Base Cutoff Current | IEBO | 1.9 | mAdc | VEB = 6.0 V, IC = 0 | 4 | ||
| Collector-Base Breakdown Voltage | V(BR)CBO | 50 | Vdc | IC = 10 A, IE = 0 | 4 | ||
| Collector-Emitter Breakdown Voltage | V(BR)CEO | 50 | Vdc | IC = 2.0 mA, IB = 0 | 4 | ||
| Collector-Base Voltage | VCBO | 50 | Vdc | TA = 25°C | 1 | ||
| Collector-Emitter Voltage | VCEO | 50 | Vdc | TA = 25°C | 1 | ||
| Collector Current | IC | 100 | mAdc | TA = 25°C | 1 | ||
| Total Device Dissipation (one junction heated) | PD | 187 | mW | TA = 25°C, FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Total Device Dissipation (one junction heated) | PD | 256 | mW | TA = 25°C, FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Derate above 25°C (one junction heated) | 1.5 | mW/°C | FR-4 @ Minimum Pad (Note 1) | 1 | |||
| Derate above 25°C (one junction heated) | 2 | mW/°C | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | |||
| Thermal Resistance Junction-to-Ambient (one junction heated) | RθJA | 670 | °C/W | FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Thermal Resistance Junction-to-Ambient (one junction heated) | RθJA | 490 | °C/W | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Total Device Dissipation (both junctions heated) | PD | 250 | mW | TA = 25°C, FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Total Device Dissipation (both junctions heated) | PD | 385 | mW | TA = 25°C, FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Derate above 25°C (both junctions heated) | 2 | mW/°C | FR-4 @ Minimum Pad (Note 1) | 1 | |||
| Derate above 25°C (both junctions heated) | 3 | mW/°C | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | |||
| Thermal Resistance Junction-to-Ambient (both junctions heated) | RθJA | 493 | °C/W | FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Thermal Resistance Junction-to-Ambient (both junctions heated) | RθJA | 325 | °C/W | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Thermal Resistance Junction-to-Lead (both junctions heated) | RθJL | 188 | °C/W | FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Thermal Resistance Junction-to-Lead (both junctions heated) | RθJL | 208 | °C/W | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Junction and Storage Temperature | TJ, Tstg | -55 | 150 | °C | 1 |
CAD (KiCad official)
- Symbol:
LMUN5316DW1T1G - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
lmun5316dw1t1g-etched.step/lmun5316dw1t1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lmun5316dw1t1g.step/lmun5316dw1t1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (29 pp, sha256
6e6d003c66003538, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).