component

LMUN5312DW1T1G

Public Made by Adom

by adom

LRC Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorslmun5312dw1t1gfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 20d ago
viewers lmun5312dw1t1g: viewers · Ray 20d ago
lmun5312dw1t1g-etched.glb lmun5312dw1t1g: factory component page (tier=lcsc) · Ray 20d ago
lmun5312dw1t1g-etched.step lmun5312dw1t1g: factory component page (tier=lcsc) · Ray 20d ago
lmun5312dw1t1g-hero.glb lmun5312dw1t1g: hero GLB from the etched model (keeps the MPN mark) · Ray 20d ago
lmun5312dw1t1g-hero.overlay.json Publish 0.1.0 · Ray 20d ago
lmun5312dw1t1g.glb Publish 0.1.0 · Ray 20d ago
lmun5312dw1t1g.kicad_mod Publish 0.1.0 · Ray 20d ago
lmun5312dw1t1g.kicad_sym Publish 0.1.0 · Ray 20d ago
lmun5312dw1t1g.lbr Publish 0.1.0 · Ray 20d ago
lmun5312dw1t1g.step Publish 0.1.0 · Ray 20d ago
package.json Publish 0.1.0 · Ray 20d ago
page.json Set visibility: public · Ray 20d ago
README.md Publish 0.1.0 · Ray 20d ago

LMUN5312DW1T1G

LRC · Digital Transistors · SOT-363

LMUN5312DW1T1G from LRC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EMITTER 2 passive Emitter terminal of transistor Q2 (NPN) in the dual bias resistor transistor, which has an integrated base-emitter and series base resistor network (R1 = 22 kΩ, R2 = 22 kΩ for LMUN5312DW1T1G).
2 BASE 2 passive Base terminal of transistor Q2, which connects to the internal series base resistor R1 of the monolithic bias network.
3 COLLECTOR 1 passive Collector terminal of transistor Q1 (PNP) in the dual bias resistor transistor, with a maximum collector current of 100 mA and collector-emitter voltage of 50 V per the device ratings.
4 EMITTER 1 passive Emitter terminal of transistor Q1 (PNP) in the dual bias resistor transistor, which has an integrated base-emitter resistor network.
5 BASE 1 passive Base terminal of transistor Q1, which connects to the internal series base resistor R1 of the monolithic bias network.
6 COLLECTOR 2 passive Collector terminal of transistor Q2 (NPN) in the dual bias resistor transistor, with a maximum collector current of 100 mA and collector-emitter voltage of 50 V per the device ratings.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-363
Category Transistors/Thyristors
Pins 6

CAD (KiCad official)

  • Symbol: LMUN5312DW1T1G
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SOT-363 (KiCad packages3D, STEP)
  • 3D model files: lmun5312dw1t1g-etched.step / lmun5312dw1t1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmun5312dw1t1g.step / lmun5312dw1t1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (30 pp, sha256 5288369b8d8d0295, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF