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LMUN5311DW1T1G
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LRC Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LMUN5311DW1T1G
LRC · Digital Transistors · SOT-363
LMUN5311DW1T1G from LRC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EMITTER 2 | passive | Emitter of transistor Q2 (NPN) in the dual BRT; the device is rated for VCEO 50 Vdc and collector current 100 mAdc. |
| 2 | BASE 2 | passive | Base of transistor Q2 (NPN), which drives the integrated bias network (R1 = 10 kΩ series base resistor and R2 = 10 kΩ base-emitter resistor for LMUN5311DW1T1G). |
| 3 | COLLECTOR 1 | passive | Collector of transistor Q1 (PNP) in the dual BRT; the device is rated for VCBO 50 Vdc and collector current 100 mAdc. |
| 4 | EMITTER 1 | passive | Emitter of transistor Q1 (PNP) in the dual BRT, with the same 50 V and 100 mA ratings as the device. |
| 5 | BASE 1 | passive | Base of transistor Q1 (PNP), which drives the integrated bias network (R1 = 10 kΩ series base resistor and R2 = 10 kΩ base-emitter resistor for LMUN5311DW1T1G). |
| 6 | COLLECTOR 2 | passive | Collector of transistor Q2 (NPN) in the dual BRT; the device is rated for VCBO 50 Vdc and collector current 100 mAdc. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
CAD (KiCad official)
- Symbol:
LMUN5311DW1T1G - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
lmun5311dw1t1g-etched.step/lmun5311dw1t1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lmun5311dw1t1g.step/lmun5311dw1t1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (30 pp, sha256
5288369b8d8d0295, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LMUN5311DW1T1G
**LRC** · Digital Transistors · SOT-363
LMUN5311DW1T1G from LRC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EMITTER 2 | passive | Emitter of transistor Q2 (NPN) in the dual BRT; the device is rated for VCEO 50 Vdc and collector current 100 mAdc. |
| 2 | BASE 2 | passive | Base of transistor Q2 (NPN), which drives the integrated bias network (R1 = 10 kΩ series base resistor and R2 = 10 kΩ base-emitter resistor for LMUN5311DW1T1G). |
| 3 | COLLECTOR 1 | passive | Collector of transistor Q1 (PNP) in the dual BRT; the device is rated for VCBO 50 Vdc and collector current 100 mAdc. |
| 4 | EMITTER 1 | passive | Emitter of transistor Q1 (PNP) in the dual BRT, with the same 50 V and 100 mA ratings as the device. |
| 5 | BASE 1 | passive | Base of transistor Q1 (PNP), which drives the integrated bias network (R1 = 10 kΩ series base resistor and R2 = 10 kΩ base-emitter resistor for LMUN5311DW1T1G). |
| 6 | COLLECTOR 2 | passive | Collector of transistor Q2 (NPN) in the dual BRT; the device is rated for VCBO 50 Vdc and collector current 100 mAdc. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
## CAD (KiCad official)
- Symbol: `LMUN5311DW1T1G`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files: `lmun5311dw1t1g-etched.step` / `lmun5311dw1t1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmun5311dw1t1g.step` / `lmun5311dw1t1g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589952068623495168) (30 pp, sha256 `5288369b8d8d0295`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lmun5311dw1t1g-datasheet.pdf)