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LMUN5214DW1T1G

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LRC Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LMUN5214DW1T1G

LRC · Digital Transistors · SOT-363

LMUN5214DW1T1G from LRC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EMITTER 2 passive Emitter of transistor Q2 in the dual BRT (NPN with monolithic bias resistors); the datasheet gives common Q1/Q2 ratings of V_CEO 50 Vdc and I_C 100 mAdc maximum.
2 BASE 2 input Base of transistor Q2, which drives the internal series base resistor R1 (10 kΩ for LMUN5214DW1T1G); the datasheet gives no separate absolute limit for this pin.
3 COLLECTOR 1 passive Collector of transistor Q1 in the dual BRT; the datasheet gives common Q1/Q2 ratings of V_CBO 50 Vdc and I_C 100 mAdc maximum.
4 EMITTER 1 passive Emitter of transistor Q1 in the dual BRT; the datasheet gives common Q1/Q2 ratings of V_CEO 50 Vdc and I_C 100 mAdc maximum.
5 BASE 1 input Base of transistor Q1, which drives the internal series base resistor R1 (10 kΩ for LMUN5214DW1T1G); the datasheet gives no separate absolute limit for this pin.
6 COLLECTOR 2 passive Collector of transistor Q2 in the dual BRT; the datasheet gives common Q1/Q2 ratings of V_CBO 50 Vdc and I_C 100 mAdc maximum.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-363
Category Transistors/Thyristors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input resistor R1 (LMUN5214DW1T1G) R1 7 10 13 kΩ 5
Resistor ratio R1/R2 (LMUN5214DW1T1G) R1 /R2 0.17 0.21 0.25 5
Collector-Base Cutoff Current I CBO 100 nAdc V CB = 50 V, I E = 0 3
Collector-Emitter Cutoff Current I CEO 500 nAdc V CE = 50 V, I B = 0 3
Emitter-Base Cutoff Current I EBO 0.2 mAdc V EB = 6.0 V, I C = 0 3
Collector-Base Breakdown Voltage V (BR)CBO 50 Vdc I C = 10 µA, I E = 0 3
Collector-Emitter Breakdown Voltage V (BR)CEO 50 Vdc I C = 2.0 mA, I B = 0 3
DC Current Gain h FE 80 140 V CE = 10 V, I C = 5.0 mA 4
Collector-Emitter Saturation Voltage V CE(sat) 0.25 Vdc I C = 10 mA, I B = 0.3 mA 4
Output Voltage (on) V OL 0.2 Vdc V CC = 5.0 V, R L = 1.0 kΩ; V B = 2.5 V (other V B conditions 3.5 V, 5.5 V, 4.0 V listed for other devices) 4
Output Voltage (off) V OH 4.9 Vdc 4
Total Device Dissipation (one junction heated, TA = 25°C, FR-4 @ minimum pad) P D 187 mW One junction heated, TA = 25°C, FR-4 @ Minimum Pad 1
Total Device Dissipation (one junction heated, TA = 25°C, FR-4 @ 1.0 x 1.0 inch pad) P D 256 mW One junction heated, TA = 25°C, FR-4 @ 1.0 x 1.0 inch Pad 1
Total Device Dissipation (both junctions heated, TA = 25°C, FR-4 @ minimum pad) P D 250 mW Both junctions heated, TA = 25°C, FR-4 @ Minimum Pad 1
Total Device Dissipation (both junctions heated, TA = 25°C, FR-4 @ 1.0 x 1.0 inch pad) P D 385 mW Both junctions heated, TA = 25°C, FR-4 @ 1.0 x 1.0 inch Pad 1
Thermal Resistance Junction-to-Ambient (one junction heated) R θJA 670 °C/W One junction heated, FR-4 @ Minimum Pad 1
Thermal Resistance Junction-to-Ambient (one junction heated) R θJA 490 °C/W One junction heated, FR-4 @ 1.0 x 1.0 inch Pad 1
Thermal Resistance Junction-to-Ambient (both junctions heated) R θJA 493 °C/W Both junctions heated, FR-4 @ Minimum Pad 1
Thermal Resistance Junction-to-Ambient (both junctions heated) R θJA 325 °C/W Both junctions heated, FR-4 @ 1.0 x 1.0 inch Pad 1
Thermal Resistance Junction-to-Lead (both junctions heated) R θJL 188 °C/W Both junctions heated, FR-4 @ Minimum Pad 1
Thermal Resistance Junction-to-Lead (both junctions heated) R θJL 208 °C/W Both junctions heated, FR-4 @ 1.0 x 1.0 inch Pad 1
Collector-Base Voltage V CBO 50 Vdc Common for Q1 and Q2, TA = 25°C 1
Collector-Emitter Voltage V CEO 50 Vdc Common for Q1 and Q2, TA = 25°C 1
Collector Current I C 100 mAdc Common for Q1 and Q2, TA = 25°C 1
Junction and Storage Temperature T J , T stg -55 150 °C 1

CAD (KiCad official)

  • Symbol: LMUN5214DW1T1G
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SOT-363 (KiCad packages3D, STEP)
  • 3D model files: lmun5214dw1t1g-etched.step / lmun5214dw1t1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmun5214dw1t1g.step / lmun5214dw1t1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (10 pp, sha256 2098411c1ec60859, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF