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LMTL3N06

Public Made by Adom

by adom

Leiditech MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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lmtl3n06-etched.step lmtl3n06: factory component page (tier=lcsc) · Ray 13d ago
lmtl3n06-hero.glb lmtl3n06: hero GLB from the etched model (keeps the MPN mark) · Ray 13d ago
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LMTL3N06

Leiditech · MOSFETs · SOT-23

LMTL3N06 from Leiditech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate, with an absolute maximum gate-source voltage of ±20 V and a gate threshold voltage of 1.2 V to 2.5 V at VDS=VGS, ID=250uA.
2 S passive Source, with a continuous source current of up to 2.3 A and a body-diode forward voltage of up to 1.2 V at IS=1A.
3 D passive Drain, rated for a 60 V drain-source voltage and a 3.0 A continuous drain current at TA=25℃ (9.2 A pulsed).

Key specifications

Parameter Value
Manufacturer Leiditech
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: LMTL3N06
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: lmtl3n06-etched.step / lmtl3n06-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmtl3n06.step / lmtl3n06.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Leiditech datasheet (5 pp, sha256 3ab28ef6a669d935, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF