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LMR54410FDBVR

Public Made by Adom

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Texas Instruments DC-DC Converters, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs lmr54410fdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers lmr54410fdbvr: viewers · Ray 1mo ago
lmr54410fdbvr-etched.fit.json lmr54410fdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lmr54410fdbvr-etched.glb lmr54410fdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lmr54410fdbvr-etched.step lmr54410fdbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
lmr54410fdbvr.glb Publish 0.1.0 · Ray 1mo ago
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lmr54410fdbvr.step Publish 0.1.0 · Ray 1mo ago
package.json lmr54410fdbvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json lmr54410fdbvr: specified limits as data (metadata.characteristics, 30 rows from the datasheet) · Ray 26d ago
README.md lmr54410fdbvr: specified limits as data (metadata.characteristics, 30 rows from the datasheet) · Ray 26d ago

LMR54410FDBVR

Texas Instruments · DC-DC Converters · SOT-23-6

LMR54410FDBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CB passive Bootstrap capacitor connection for the high-side FET driver; connect a 100nF quality capacitor between this pin and the SW pin.
2 GND power_in Power ground pin; internally connected to the source of the low-side FET; connect to system ground and the ground sides of CIN and COUT with minimum distance to CIN.
3 FB input Feedback input of the converter; connect resistor voltage divider to set output voltage; do not short-circuit to ground during operation.
4 EN input Precision enable input; cannot be left floating; high level = on, low level = off; can be connected to VIN; allows adjustable UVLO through external resistor divider.
5 VIN power_in Power supply input for internal bias LDO and high-side FET; connect to input power supply (4-36V) and input bypass capacitor CIN; bypass capacitor must be directly connected to this pin and GND.
6 SW power_out Switch output node; internally connected to the source of the high-side FET and drain of the low-side FET; connect to power inductor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-6
Category Power Management (PMIC)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN_UVLO rising threshold VIN_UVLO 3.55 3.75 4 V 5
VIN_UVLO falling threshold VIN_UVLO 3.25 3.45 3.65 V 5
Shutdown quiescent current, measured at VIN pin ISD 3 10 µA VEN = 0V 5
Enable input high threshold (VOUT enable) VEN-VOUT-H 1.1 1.23 1.36 V VENABLE rising 5
Enable input low threshold (VOUT enable) VEN-VOUT-L 0.95 1.1 1.22 V VENABLE falling 5
Enable input leakage current ILKG-EN 10 200 nA VEN = 3.3V 5
Feedback voltage VFB 0.79 0.8 0.81 V 5
Internal oscillator frequency FOSC 0.935 1.1 1.265 MHz 5
High-side current limit, LMR54410 ISC 1.25 1.6 1.9 A Open-loop production test 5
Low-side current limit, LMR54410 ILS-LIMIT 0.9 1.1 1.3 A Open-loop production test 5
Input voltage operating range VIN 4 36 V 7
VOUT adjustable output regulation, FPWM operation VOUT -1.5 1.5 % FPWM operation; VIN = 24V, IOUT = 0A to full load 7
VIN to GND -0.3 45 V DC maximum 4
EN to GND -0.3 V Max = VIN+0.3 V 4
FB to GND -0.3 5.5 V 4
SW to GND -0.3 V Max = VIN+0.3 V 4
SW to PGND transient -5 V Transient less than 10 ns; max = VIN+0.3 V 4
CBOOT to SW -0.3 5.5 V 4
Junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
VIN to GND operating voltage 4 36 V 4
EN to GND 0 V Maximum is VIN; must not exceed VIN by more than 0.3V 4
Output voltage VOUT VOUT 0.8 28 V 4
Output current, LMR54410 0 1 A 4
Operating junction temperature TJ -40 150 °C 4
Junction-to-ambient thermal resistance RθJA 173 °C/W 4-layer JEDEC board per JESD 51-7; not for design use 5
Junction-to-case (top) thermal resistance RθJC(top) 116 °C/W 5
Junction-to-board thermal resistance RθJB 31 °C/W 5
Junction-to-top characterization parameter ψJT 20 °C/W 5
Junction-to-board characterization parameter ψJB 30 °C/W 5

CAD (KiCad official)

  • Symbol: LMR54410FDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: lmr54410fdbvr-etched.step / lmr54410fdbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmr54410fdbvr.step / lmr54410fdbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 aa5bab2b39f730aa, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF