component

LMR51420XDDCR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LMR51420XDDCR

Texas Instruments · DC-DC Converters · SOT-23-6

LMR51420XDDCR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Power ground terminal connected to the low-side FET source; must be connected to system ground with the shortest possible path to the input bypass capacitor.
2 SW power_out Switching output node connected to the high-side FET source and low-side FET drain; connect this pin to the power inductor.
3 VIN power_in Supply input terminal for internal bias LDO and high-side FET; connect directly to input supply with input bypass capacitors.
4 FB input Feedback input for voltage regulation through external resistor divider; never short to ground during operation.
5 EN input Precision enable input for ON/OFF control with HIGH = on and LOW = off; cannot be left floating and allows adjustable UVLO through external resistor divider.
6 CB power_out Bootstrap capacitor connection for high-side FET gate driver; connect a 100-nF high-quality ceramic capacitor from this pin to the SW pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-6
Category Power Management (PMIC)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN quiescent current (non-switching) IQ(VIN) 40 65 µA VEN = 3 V, PFM variant only 5
VIN shutdown supply current ISD(VIN) 3 15 µA VEN = 0 V 5
VIN UVLO rising threshold VINUVLO(R) 3.89 4.5 V VIN rising 5
VIN UVLO falling threshold VINUVLO(F) 3.35 3.58 V VIN falling 5
EN voltage rising threshold VEN(R) 1.1 1.227 1.36 V EN rising, enable switching 5
EN voltage falling threshold VEN(F) 0.95 1.08 1.22 V EN falling, disable switching 5
EN pin sourcing current post EN rising threshold IEN(P2) 10 200 nA VEN = 3 V 5
Reference voltage Vfb 0.591 0.6 0.609 V 5
FB input leakage current IFB(LKG) 0.8 50 nA VFB = 1.2 V 5
Switching frequency, CCM operation fSW1(CCM) 450 500 560 kHz 500-kHz trim option 5
Internal fixed soft-start time tSS 3.2 4 5.4 ms 5
High-side peak current limit IHS_PK(OC) 2.7 3.5 5.1 A LM51420 5
Low-side valley current limit ILS_V(OC) 1.7 2.5 3.4 A LM51420 6
VIN operating input voltage range VIN 4.5 36 V 6
Adjustable output voltage regulation (PFM operation) VOUT -1.5 2.5 % PFM operation; VIN = 24 V, IOUT = 0 A to full load 6
Maximum switch duty cycle DMAX 98 % 6
VIN to GND input voltage VIN 4.5 36 V 4
EN pin voltage EN 0 V 4
FB pin voltage FB 0 4.5 V 4
Output voltage VOUT 0.6 V 4
Output current Iout 2 A 4
Operating junction temperature TJ -40 150 °C 4
Input voltage VIN VIN -0.3 38 V 4
Input voltage EN EN -0.3 V 4
Input voltage FB FB -0.3 5.5 V 4
Output voltage SW, DC SW -0.3 38 V DC 4
Output voltage SW, transient SW -3 38 V transient < 20 ns 4
Output voltage CB CB -0.3 43.5 V 4
CB to SW voltage CB to SW -0.3 5.5 V 4
Junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
VIN UVLO hysteresis VINUVLO(H) 0.3 V 5
High-side MOSFET on-resistance RDSON(HS) 0.12 Ω TJ = 25℃ 5
Low-side MOSFET on-resistance RDSON(LS) 0.07 Ω TJ = 25℃ 5
Minimum ON pulse width tON(min) 70 ns VIN = 12 V, IOUT = 2 A 5
Maximum ON pulse width tON(max) 6.76 µs VIN = 12 V, IOUT = 2 A 5
Minimum OFF pulse width tOFF(min) 150 ns VIN = 4.5 V 5
Zero-cross detection current threshold IZC 0.02 A 6
Thermal shutdown threshold TJ(SD) 163 °C Temperature rising 6
Thermal shutdown hysteresis TJ(HYS) 22 °C 6
VIN quiescent current (non-switching), system ISUPPLY 40 µA VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A, RFBT = 1 MΩ, PFM variant 6
FB pin voltage to trip short-circuit hiccup mode VHC 0.24 V 6
Switch voltage dead-time tD 6.5 ns 6
Thermal shutdown temperature TSD 163 °C Shutdown temperature 6
Thermal shutdown temperature TSD 141 °C Recovery temperature 6
Junction-to-ambient thermal resistance RθJA 107.8 °C/W DDC (SOT-23-6), JESD 51-7, 4-layer JEDEC board 5
Junction-to-case (top) thermal resistance RθJC(top) 52.4 °C/W DDC (SOT-23-6), JESD 51-7, 4-layer JEDEC board 5
Junction-to-board thermal resistance RθJB 23.3 °C/W DDC (SOT-23-6), JESD 51-7, 4-layer JEDEC board 5
Junction-to-top characterization parameter ψJT 9.3 °C/W DDC (SOT-23-6), JESD 51-7, 4-layer JEDEC board 5
Junction-to-board characterization parameter ψJB 23 °C/W DDC (SOT-23-6), JESD 51-7, 4-layer JEDEC board 5

CAD (KiCad official)

  • Symbol: LMR51420XDDCR
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: lmr51420xddcr-etched.step / lmr51420xddcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmr51420xddcr.step / lmr51420xddcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 0ad3d2ef438f42ca, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF