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Contents

README

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LMR51410YDBVR

Texas Instruments · Others · SOT-23-6

LMR51410YDBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CB passive Bootstrap capacitor connection for the high-side FET driver; connect a high quality 100nF capacitor from this pin to the SW pin.
2 GND power_in Power ground connected to the source of the low-side FET internally; connect to system ground and the ground side of CIN and COUT, with the path to CIN as short as possible.
3 FB input Feedback input to the converter; connect a resistor divider to set the output voltage and never short this terminal to ground during operation.
4 EN input Precision enable input (High = on, Low = off) that must not be floated, can be tied to VIN, and allows an adjustable UVLO via an external resistor divider.
5 VIN power_in Supply input to the internal bias LDO and high-side FET (4V to 42V recommended); connect to the input supply with input bypass capacitors CIN directly at this pin and GND.
6 SW power_out Switching output of the converter, internally connected to the source of the high-side FET and drain of the low-side FET; connect to the power inductor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-6
Category Others
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN quiescent current (non-switching) IQ(VIN) 26.5 40 µA VEN = 3V, PFM Variant Only 5
VIN shutdown supply current ISD(VIN) 0.8 3 µA VEN = 0V 5
VIN UVLO rising threshold VIN_UVLO(R) 3.82 4 V VIN rising 5
VIN UVLO falling threshold VIN_UVLO(F) 3.4 3.56 V VIN falling 5
VIN UVLO hysteresis VIN_UVLO(H) 0.25 V 5
EN voltage rising threshold VEN(R) 1.1 1.227 1.36 V EN rising, enable switching 5
EN voltage falling threshold VEN(F) 0.85 1 1.15 V EN falling, disable switching 5
EN pin sourcing current post EN rising threshold IEN(P2) 10 50 nA VEN = 3V 5
Reference voltage VFB 0.788 0.8 0.812 V 5
FB input leakage current IFB(LKG) 0.2 nA VFB = 0.8V 5
Switching frequency, CCM operation, Y version fSW(CCM) 0.935 1.1 1.265 MHz "Y" Version 5
Internal fixed soft-start time tSS 2.3 ms 5
High-side MOSFET on-resistance RDSON(HS) 0.7 Ω VIN = 12V, TJ = 25°C 5
Low-side MOSFET on-resistance RDSON(LS) 0.36 Ω VIN = 12V, TJ = 25°C 5
Minimum ON pulse width tON_MIN 80 ns VIN = 12V, IOUT = 0.1A 5
Maximum ON pulse width tON_MAX 5 µs VIN = 12V, IOUT = 0.5A 5
Minimum OFF pulse width tOFF_MIN 200 ns VIN = 5V 6
High-side peak current limit IHS_PK(OC) 1.25 1.6 1.95 A LMR51410 6
Low-side valley current limit ILS_V(OC) 0.9 1.1 1.3 A LMR51410 6
Zero-cross detection current threshold IZC 0 A 6
Thermal shutdown threshold TJ(SD) 165 °C Junction temperature rising 6
Thermal shutdown hysteresis TJ(HYS) 20 °C 6
Operating input voltage range VIN 4 42 V System characteristics 6
Adjustable output voltage regulation VOUT -1.5 2.5 % PFM operation 6
Input supply current when in regulation ISUPPLY 38 µA VIN = 24V, VOUT = 5V, IOUT = 0A, RFBB = 22.1kΩ, PFM variant 6
Maximum switch duty cycle DMAX 98 % 6
FB pin voltage required to trip short-circuit hiccup mode VHC 0.32 V 6
Time between current-limit hiccup burst THICCUP 150 ms 6
Input voltage VIN to GND VIN -0.3 45 V 4
Input voltage EN to GND EN -0.3 V max = VIN + 0.3 V 4
Input voltage FB to GND FB -0.3 5.5 V 4
Output voltage SW to GND SW -0.3 45 V 4
Output voltage SW to GND less than 10ns transients SW -5 50 V less than 10ns transients 4
Output voltage CBOOT to SW CBOOT -0.3 5.5 V 4
Junction temperature TJ -40 150 °C 4
Storage temperature Tstg -55 150 °C 4
ESD HBM V(ESD) -2500 2500 V Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 4
ESD CDM V(ESD) -750 750 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 4
Input voltage VIN to GND VIN 4 42 V 4
Input voltage EN EN 0 V max = VIN 4
Input voltage FB FB 0 4.5 V 4
Output voltage VOUT VOUT 0.8 28 V 4
Output current Iout(LMR51410) Iout 1 A 4
Operating junction temperature TJ -40 150 °C 4
Junction-to-ambient thermal resistance RθJA 147.8 °C/W DBV (SOT-23-6), 6 pins 5
Junction-to-ambient thermal resistance with EVM RθJA(Effective) 95 °C/W DBV (SOT-23-6), 6 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 71.1 °C/W DBV (SOT-23-6), 6 pins 5
Junction-to-board thermal resistance RθJB 36.6 °C/W DBV (SOT-23-6), 6 pins 5
Junction-to-top characterization parameter ψJT 14.2 °C/W DBV (SOT-23-6), 6 pins 5
Junction-to-board characterization parameter ψJB 36.4 °C/W DBV (SOT-23-6), 6 pins 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) must be used 21

CAD (KiCad official)

  • Symbol: LMR51410YDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: lmr51410ydbvr-etched.step / lmr51410ydbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmr51410ydbvr.step / lmr51410ydbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 a61ac445a7c8c97e, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF