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LMR33630BDDAR

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Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LMR33630BDDAR

Texas Instruments · DC-DC Converters · SOIC-8-EP

LMR33630BDDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Power ground terminal; connect to system ground and AGND, and to the bypass capacitor with short wide traces.
2 VIN power_in Input supply to the regulator; connect a high-quality bypass capacitor or capacitors directly to this pin and PGND.
3 EN input Enable input to the regulator; high = ON, low = OFF, can be connected directly to VIN, must not be left floating.
4 PG output Open-drain power-good flag output; connect to a suitable voltage supply through a current-limiting resistor, high = power OK, low = power bad, pulls low when EN is low, can be left open when not used.
5 FB input Feedback input to the regulator; connect to the tap point of the feedback voltage divider, must not be left floating or grounded.
6 VCC power_out Internal 5-V LDO output used as supply to internal control circuits; do not connect to external loads other than the power-good pull-up, connect a high-quality 1-µF capacitor from this pin to GND.
7 BOOT power_in Bootstrap supply voltage for the internal high-side driver; connect a high-quality 100-nF capacitor from this pin to the SW pin.
8 SW power_out Regulator switch node; connect to the power inductor.
9 AGND power_in Analog ground for the regulator and system, ground reference for internal references and logic; on the HSOIC package the bottom thermal pad serves as both the AGND connection and a thermal connection to the heat-sink ground plane and must be soldered to a ground plane for good electrical and thermal performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN to PGND -0.3 38 V 5
EN to AGND -0.3 V 5
FB to AGND -0.3 5.5 V 5
PG to AGND 0 22 V 5
AGND to PGND -0.3 0.3 V 5
SW to PGND -0.3 V 5
SW to PGND less than 100-ns transients -3.5 38 V less than 100-ns transients 5
BOOT to SW -0.3 5.5 V 5
VCC to AGND -0.3 5.5 V 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -55 150 °C 5
Human-body model (HBM) electrostatic discharge V(ESD) -2500 2500 V 5
Charged-device model (CDM) electrostatic discharge V(ESD) -750 750 V 5
Input voltage VIN to PGND 3.8 36 V 5
EN 0 V 5
PG 0 18 V 5
Adjustable output voltage VOUT 1 24 V 5
Output current IOUT 0 3 A 5
Non-switching input current, measured at VIN pin IQ 24 34 µA VFB = 1.2 V 6
Shutdown quiescent current, measured at VIN pin ISD 5 10 µA EN = 0 6
Minimum operating input voltage VIN 3.8 V 6
EN input level required to start switching VEN-H 1.2 1.231 1.26 V Rising threshold 6
Internal LDO output voltage appearing at VCC pin VCC 4.75 5 5.25 V 6 V ≤ VIN ≤ 36 V 6
Feedback voltage; ADJ option VFB 0.985 1 1.015 V 6
Current into FB pin; ADJ option IFB 0.2 50 nA FB = 1 V 6
High-side current limit ISC 3.85 4.5 5.05 A LMR33630 6
Low-side current limit ILIMIT 2.9 3.5 4.1 A LMR33630 6
Internal soft-start time tSS 2.9 4 6 ms 7
Power-good upper threshold, rising, % of FB voltage VPG-HIGH-UP 105 107 110 % 7
Power-good upper threshold, falling, % of FB voltage VPG-HIGH-DN 103 105 108 % 7
Power-good lower threshold, rising, % of FB voltage VPG-LOW-UP 92 94 97 % 7
Power-good lower threshold, falling, % of FB voltage VPG-LOW-DN 90 92 95 % 7
Power-good glitch filter delay tPG 60 170 µs 7
Power-good flag RDSON RPG 76 150 Ω VIN = 12 V, VEN = 4 V 7
Power-good flag RDSON RPG 35 60 Ω VEN = 0 V 7
Switching frequency, B version ƒSW 1.2 1.4 1.6 MHz B version 7
High-side MOSFET ON-resistance, DDA package RDS-ON-HS 95 160 mΩ DDA package 7
Low-side MOSFET ON-resistance, DDA package RDS-ON-LS 66 110 mΩ DDA package 7
Minimum switch on-time, DDA package tON-MIN 75 108 ns DDA package 7
Minimum switch off-time, DDA package tOFF-MIN 50 85 ns DDA package 7
Maximum switch on-time tON-MAX 7 9 µs 7
Operating input voltage range VIN 3.8 36 V VOUT = 3.3 V, IOUT = 0 A 8
Output voltage regulation for VOUT = 5 V VOUT -1.5 2.5 % VIN = 7 V to 36 V, IOUT = 0 A to max. load 8
Output voltage regulation for VOUT = 5 V VOUT -1.5 1.5 % VIN = 7 V to 36 V, IOUT = 1 A to max. load 8
Output voltage regulation for VOUT = 3.3 V VOUT -1.5 2.5 % VIN = 3.8 V to 36 V, IOUT = 0 A to max. load 8
Output voltage regulation for VOUT = 3.3 V VOUT -1.5 1.5 % VIN = 3.8 V to 36 V, IOUT = 1 A to max. load 8
Junction-to-ambient thermal resistance RθJA 42.9 °C/W 6
Junction-to-case (top) thermal resistance RθJC(top) 54 °C/W 6
Junction-to-board thermal resistance RθJB 13.6 °C/W 6
EN input level required to turn on internal LDO, rising threshold VEN-VCC-H 1 V 6
EN input level required to turn off internal LDO, falling threshold VEN-VCC-L 0.3 V 6
Hysteresis below VEN-H, falling VEN-HYS 100 mV Hysteresis below VEN-H; falling 6
Bootstrap voltage undervoltage lock-out threshold VBOOT-UVLO 2.2 V 6
Minimum peak inductor current, LMR33630 IPEAK-MIN 0.69 A 6
Input supply current when in regulation ISUPPLY 25 µA VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A, RFBT = 1 MΩ 8
Dropout voltage (VIN – VOUT) VDROP 150 mV VOUT = 5 V, IOUT = 1A; dropout at -1% of regulation, fSW = 140 kHz 8
Maximum switch duty cycle DMAX 98 % VIN = VOUT = 12 V, IOUT = 1 A 8
FB pin voltage required to trip short-circuit hiccup mode VHC 0.4 V 8
Thermal shutdown temperature, shutdown TSD 165 °C 8
Thermal shutdown temperature, recovery TSD 148 °C 8

CAD (KiCad official)

  • Symbol: LMR33630BDDAR
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: lmr33630bddar-etched.step / lmr33630bddar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmr33630bddar.step / lmr33630bddar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (57 pp, sha256 71bca20c1f8dd624, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF