component
LMR33620CDDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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LMR33620CDDAR
Texas Instruments · DC-DC Converters · SO-8
LMR33620CDDAR from Texas Instruments, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground terminal that must connect to system ground and AGND, with bypass capacitor connected using short wide traces. |
| 2 | VIN | power_in | Input supply to the regulator, specified from 3.8 V to 36 V, with a high-quality bypass capacitor connected directly to this pin and PGND. |
| 3 | EN | input | Enable input where high turns the regulator on and low turns it off; it can be connected directly to VIN but must not float. |
| 4 | PG | output | Open-drain power-good flag output that is pulled low when EN is low or power is bad, and requires a current-limiting resistor to a supply when used. |
| 5 | FB | input | Feedback input connected to the tap point of the feedback voltage divider, which must not float or be grounded. |
| 6 | VCC | power_out | Internal 5-V LDO output used as the supply for internal control circuits, which must not drive external loads and needs a high-quality 1-µF capacitor to GND. |
| 7 | BOOT | power_out | Boot-strap supply for the internal high-side driver, connected through a high-quality 100-nF capacitor to the SW pin. |
| 8 | SW | power_out | Regulator switch node that connects to the power inductor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to PGND | VIN | -0.3 | 38 | V | 5 | ||
| EN to AGND | VEN | -0.3 | V | max VIN + 0.3 V | 5 | ||
| FB to AGND | VFB | -0.3 | 5.5 | V | 5 | ||
| PG to AGND | VPG | 0 | 22 | V | 5 | ||
| AGND to PGND | -0.3 | 0.3 | V | 5 | |||
| SW to PGND | VSW | -0.3 | V | max VIN + 0.3 V | 5 | ||
| SW to PGND transient | VSW | -3.5 | 38 | V | less than 100-ns transients | 5 | |
| BOOT to SW | VBOOT | -0.3 | 5.5 | V | 5 | ||
| VCC to AGND | VCC | -0.3 | 5.5 | V | 5 | ||
| Junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| Input voltage VIN to PGND | VIN | 3.8 | 36 | V | 5 | ||
| EN input voltage | VEN | 0 | V | max VIN | 5 | ||
| PG voltage | VPG | 0 | 18 | V | 5 | ||
| Output current | IOUT | 0 | 2 | A | 5 | ||
| Minimum operating input voltage | VIN | 3.8 | V | 6 | |||
| Non-switching input current | IQ | 24 | 34 | µA | VFB = 1.2 V | 6 | |
| Shutdown quiescent current | ISD | 5 | 10 | µA | EN = 0 | 6 | |
| EN input level to start switching, rising threshold | VEN-H | 1.2 | 1.231 | 1.26 | V | Rising threshold | 6 |
| Internal LDO output voltage at VCC | VCC | 4.75 | 5 | 5.25 | V | 6 V ≤ VIN ≤ 36 V | 6 |
| High-side current limit | ISC | 2.9 | 3.5 | 4 | A | LMR33620 | 6 |
| Low-side current limit | ILIMIT | 1.95 | 2.45 | 2.9 | A | LMR33620 | 6 |
| Internal soft-start time | tSS | 2.9 | 4 | 6 | ms | 7 | |
| Power-good upper threshold rising | VPG-HIGH-UP | 105 | 107 | 110 | % of FB voltage | rising % of FB voltage | 7 |
| Power-good upper threshold falling | VPG-HIGH-DN | 103 | 105 | 108 | % of FB voltage | falling % of FB voltage | 7 |
| Power-good lower threshold rising | VPG-LOW-UP | 92 | 94 | 97 | % of FB voltage | rising % of FB voltage | 7 |
| Power-good lower threshold falling | VPG-LOW-DN | 90 | 92 | 95 | % of FB voltage | falling % of FB voltage | 7 |
| Power-good glitch filter delay | tPG | 60 | 170 | µs | 7 | ||
| Power-good flag RDSON | RPG | 76 | 150 | Ω | VIN = 12 V, VEN = 4 V | 7 | |
| Power-good flag RDSON | RPG | 35 | 60 | Ω | VEN = 0 V | 7 | |
| Switching frequency C version, DDA package | fSW | 1.8 | 2.1 | 2.4 | MHz | C version, DDA package | 7 |
| High-side MOSFET ON-resistance DDA package | RDS-ON-HS | 95 | 160 | mΩ | DDA package | 7 | |
| Low-side MOSFET ON-resistance DDA package | RDS-ON-LS | 66 | 110 | mΩ | DDA package | 7 | |
| Minimum switch on-time DDA package | tON-MIN | 75 | 108 | ns | DDA package | 7 | |
| Minimum switch off-time DDA package | tOFF-MIN | 50 | 85 | ns | DDA package | 7 | |
| Maximum switch on-time | tON-MAX | 7 | 9 | µs | 7 | ||
| Operating input voltage range | VIN | 3.8 | 36 | V | VOUT = 3.3 V, IOUT = 0 A | 8 | |
| Output voltage regulation for VOUT = 5 V | VOUT | -1.5 | 2.5 | % | VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 0 A to max. load | 8 | |
| Output voltage regulation for VOUT = 5 V | VOUT | -1.5 | 1.5 | % | VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 1 A to max. load | 8 | |
| Output voltage regulation for VOUT = 3.3 V | VOUT | -1.5 | 2.5 | % | VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 0 A to max. load | 8 | |
| Output voltage regulation for VOUT = 3.3 V | VOUT | -1.5 | 1.5 | % | VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 1 A to max. load | 8 | |
| Junction-to-ambient thermal resistance DDA (HSOIC) | RθJA | 42.9 | °C/W | DDA 8 pins, 4-layer JEDEC board | 6 | ||
| Junction-to-case (top) thermal resistance DDA (HSOIC) | RθJC(top) | 54 | °C/W | DDA 8 pins | 6 | ||
| Junction-to-board thermal resistance DDA (HSOIC) | RθJB | 13.6 | °C/W | DDA 8 pins | 6 | ||
| Junction-to-top characterization parameter DDA (HSOIC) | ψJT | 4.3 | °C/W | DDA 8 pins | 6 | ||
| Junction-to-board characterization parameter DDA (HSOIC) | ψJB | 13.8 | °C/W | DDA 8 pins | 6 | ||
| Junction-to-case (bottom) thermal resistance DDA (HSOIC) | RθJC(bot) | 4.3 | °C/W | DDA 8 pins | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 9. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as | 32 |
CAD (KiCad official)
- Symbol:
LMR33620CDDAR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
lmr33620cddar-etched.step/lmr33620cddar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lmr33620cddar.step/lmr33620cddar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (59 pp, sha256
865af73e62240338, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).