component
LMR14020QDPRTQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, WSON-10-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+48@@ -0,0 +1,48 @@+# LMR14020QDPRTQ1++**Texas Instruments** · DC-DC Converters · WSON-10-EP(4x4)++LMR14020QDPRTQ1 from Texas Instruments, in a WSON-10-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | BOOT | power_out | Bootstrap capacitor connection for the high-side MOSFET gate driver; connect a quality 0.1 µF X7R or X5R capacitor rated 16 V or higher between BOOT and SW. |+| 2 | VIN | power_in | Supply input for the regulator, operating from 4 V to 40 V; the path from VIN to the high-frequency bypass capacitor CIN and GND must be kept as short as possible. |+| 3 | VIN | power_in | Supply input for the regulator (second VIN pin, same connection as pin 2), operating from 4 V to 40 V; keep the path to CIN and GND as short as possible. |+| 4 | EN | input | Enable input with an internal pull-up current source; pulling it below 1.2 V disables the device, while leaving it floating or tying it to VIN enables it, and two resistors can set the input UVLO. EN absolute maximum is 44 V and recommended range is 0 V to 40 V. |+| 5 | RT/SYNC | input | Timing resistor connection or external clock input that sets the switching frequency (200 kHz to 2.5 MHz in RT mode, 250 kHz to 2.3 MHz when synchronized); it must not be left floating or shorted to ground, and a clock with high level ≥1.7 V, low level ≤0.5 V and pulse width >30 ns is required for sync. |+| 6 | SS | input | Soft-start control pin; a capacitor from SS to GND sets the soft-start time using the internal ~3 µA charge current, and for the WSON package the maximum CSS is 4.7 nF. |+| 7 | FB | input | Feedback input connected to the output divider that sets VOUT (VREF typically 0.75 V); connect directly to VOUT for a fixed output, and do not short this pin to ground during operation. The recommended FB range is 0 V to 5 V. |+| 8 | PGOOD | output | Open-drain power-good flag that needs a pull-up of 10 kΩ to 100 kΩ to a logic rail or DC voltage, and the voltage on this pin must never exceed 7 V. |+| 9 | GND | power_in | System ground pin for the regulator, to be connected to the system ground plane. |+| 10 | SW | output | Regulator switching output, internally connected to the low-side power MOSFET, which connects to the power inductor; SW is rated from -3 V to 44 V. |+| 11 | Thermal Pad | power_in | Exposed thermal pad that is the main heat-dissipation path from the die; it must be connected to a ground layer on the PCB. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WSON-10-EP(4x4) |+| Category | Power Supply Chip |+| Pins | 11 |++## CAD (KiCad official)++- Symbol: `LMR14020QDPRTQ1`+- Footprint: `Package_SON:WSON-10-1EP_4x4mm_P0.8mm_EP2.6x3mm`+- 3D model: WSON-10-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `lmr14020qdprtq1-etched.step` / `lmr14020qdprtq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmr14020qdprtq1.step` / `lmr14020qdprtq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmr14020-q1) (37 pp, sha256 `6e24800c10410b48`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lmr14020qdprtq1-datasheet.pdf)
page.jsonadded+217@@ -0,0 +1,217 @@+{+ "slug": "lmr14020qdprtq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, WSON-10-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "lmr14020qdprtq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lmr14020qdprtq1.kicad_sym",+ "lmr14020qdprtq1.kicad_mod",+ "lmr14020qdprtq1.glb",+ "lmr14020qdprtq1.step",+ "lmr14020qdprtq1.lbr",+ "docs/hero.png",+ "docs/lmr14020qdprtq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lmr14020qdprtq1-hero.glb",+ "lmr14020qdprtq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "LMR14020QDPRTQ1",+ "manufacturer": "Texas Instruments",+ "package": "WSON-10-EP(4x4)",+ "pin_count": 11,+ "category": "Power Supply Chip",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lmr14020-q1",+ "parts": {+ "symbol": "lmr14020qdprtq1.kicad_sym",+ "footprint": "lmr14020qdprtq1.kicad_mod",+ "model_3d": "lmr14020qdprtq1-hero.glb",+ "model_3d_plain": "lmr14020qdprtq1.glb",+ "model_3d_step": "lmr14020qdprtq1-etched.step",+ "model_3d_step_plain": "lmr14020qdprtq1.step",+ "lbr": "lmr14020qdprtq1.lbr"+ },+ "distributor_links": {+ "lcsc": "C2071772",+ "digikey": "296-44760-2-ND",+ "mouser": "595-LMR14020QDPRTQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:31:09Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-44760-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-LMR14020QDPRTQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "BOOT",+ "type": "power_out",+ "description": "Bootstrap capacitor connection for the high-side MOSFET gate driver; connect a quality 0.1 µF X7R or X5R capacitor rated 16 V or higher between BOOT and SW."+ },+ {+ "number": "2",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input for the regulator, operating from 4 V to 40 V; the path from VIN to the high-frequency bypass capacitor CIN and GND must be kept as short as possible."+ },+ {+ "number": "3",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input for the regulator (second VIN pin, same connection as pin 2), operating from 4 V to 40 V; keep the path to CIN and GND as short as possible."+ },+ {+ "number": "4",+ "name": "EN",+ "type": "input",+ "description": "Enable input with an internal pull-up current source; pulling it below 1.2 V disables the device, while leaving it floating or tying it to VIN enables it, and two resistors can set the input UVLO. EN absolute maximum is 44 V and recommended range is 0 V to 40 V."+ },+ {+ "number": "5",+ "name": "RT/SYNC",+ "type": "input",+ "description": "Timing resistor connection or external clock input that sets the switching frequency (200 kHz to 2.5 MHz in RT mode, 250 kHz to 2.3 MHz when synchronized); it must not be left floating or shorted to ground, and a clock with high level ≥1.7 V, low level ≤0.5 V and pulse width >30 ns is required for sync."+ },+ {+ "number": "6",+ "name": "SS",+ "type": "input",+ "description": "Soft-start control pin; a capacitor from SS to GND sets the soft-start time using the internal ~3 µA charge current, and for the WSON package the maximum CSS is 4.7 nF."+ },+ {+ "number": "7",+ "name": "FB",+ "type": "input",+ "description": "Feedback input connected to the output divider that sets VOUT (VREF typically 0.75 V); connect directly to VOUT for a fixed output, and do not short this pin to ground during operation. The recommended FB range is 0 V to 5 V."+ },+ {+ "number": "8",+ "name": "PGOOD",+ "type": "output",+ "description": "Open-drain power-good flag that needs a pull-up of 10 kΩ to 100 kΩ to a logic rail or DC voltage, and the voltage on this pin must never exceed 7 V."+ },+ {+ "number": "9",+ "name": "GND",+ "type": "power_in",+ "description": "System ground pin for the regulator, to be connected to the system ground plane."+ },+ {+ "number": "10",+ "name": "SW",+ "type": "output",+ "description": "Regulator switching output, internally connected to the low-side power MOSFET, which connects to the power inductor; SW is rated from -3 V to 44 V."+ },+ {+ "number": "11",+ "name": "Thermal Pad",+ "type": "power_in",+ "description": "Exposed thermal pad that is the main heat-dissipation path from the die; it must be connected to a ground layer on the PCB."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package size check: the requested hint is WSON-10-EP (4x4). The datasheet's ordering table gives the; Pin 1 is BOOT for the WSON-10 package. Table 4-1 and Figure 4-2 agree on the pin numbers (FB=7, SS=6; Pin types were mapped from the datasheet's P/A/G codes to KiCad ERC classes: BOOT as power_out, SW a"+ ],+ "pages_sent": 27,+ "cost_usd": 0.1436,+ "at": "2026-10-08T15:30:50"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lmr14020-q1",+ "pages": 37,+ "sha256": "6e24800c10410b48",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 11,+ "described": 11,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lmr14020qdprtq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 3.95,+ 0.8+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ef3c2f392fea7049285bfc942095cbd03d5bb47d74597dd80d1bc887363be656",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lmr14020qdprtq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 3.95,+ 0.8+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dc28c3cf318325bd5b560bedd06cd945901c65dcc1e5a8fc5a118396f6553882",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}