component
LMR14020QDPRTQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, WSON-10-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLMR14020QDPRTQ1
Texas Instruments · DC-DC Converters · WSON-10-EP(4x4)
LMR14020QDPRTQ1 from Texas Instruments, in a WSON-10-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_out | Bootstrap capacitor connection for the high-side MOSFET gate driver; connect a quality 0.1 µF X7R or X5R capacitor rated 16 V or higher between BOOT and SW. |
| 2 | VIN | power_in | Supply input for the regulator, operating from 4 V to 40 V; the path from VIN to the high-frequency bypass capacitor CIN and GND must be kept as short as possible. |
| 3 | VIN | power_in | Supply input for the regulator (second VIN pin, same connection as pin 2), operating from 4 V to 40 V; keep the path to CIN and GND as short as possible. |
| 4 | EN | input | Enable input with an internal pull-up current source; pulling it below 1.2 V disables the device, while leaving it floating or tying it to VIN enables it, and two resistors can set the input UVLO. EN absolute maximum is 44 V and recommended range is 0 V to 40 V. |
| 5 | RT/SYNC | input | Timing resistor connection or external clock input that sets the switching frequency (200 kHz to 2.5 MHz in RT mode, 250 kHz to 2.3 MHz when synchronized); it must not be left floating or shorted to ground, and a clock with high level ≥1.7 V, low level ≤0.5 V and pulse width >30 ns is required for sync. |
| 6 | SS | input | Soft-start control pin; a capacitor from SS to GND sets the soft-start time using the internal ~3 µA charge current, and for the WSON package the maximum CSS is 4.7 nF. |
| 7 | FB | input | Feedback input connected to the output divider that sets VOUT (VREF typically 0.75 V); connect directly to VOUT for a fixed output, and do not short this pin to ground during operation. The recommended FB range is 0 V to 5 V. |
| 8 | PGOOD | output | Open-drain power-good flag that needs a pull-up of 10 kΩ to 100 kΩ to a logic rail or DC voltage, and the voltage on this pin must never exceed 7 V. |
| 9 | GND | power_in | System ground pin for the regulator, to be connected to the system ground plane. |
| 10 | SW | output | Regulator switching output, internally connected to the low-side power MOSFET, which connects to the power inductor; SW is rated from -3 V to 44 V. |
| 11 | Thermal Pad | power_in | Exposed thermal pad that is the main heat-dissipation path from the die; it must be connected to a ground layer on the PCB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(4x4) |
| Category | Power Supply Chip |
| Pins | 11 |
CAD (KiCad official)
- Symbol:
LMR14020QDPRTQ1 - Footprint:
Package_SON:WSON-10-1EP_4x4mm_P0.8mm_EP2.6x3mm - 3D model: WSON-10-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
lmr14020qdprtq1-etched.step/lmr14020qdprtq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lmr14020qdprtq1.step/lmr14020qdprtq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
6e24800c10410b48, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).