component

LMQ644A2QRXARQ1

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, VQFN-24-EP(5x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentpower management (pmic)lmq644a2qrxarq1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

LMQ644A2QRXARQ1

Texas Instruments · DC-DC Converters · VQFN-24-EP(5x4)

LMQ644A2QRXARQ1 from Texas Instruments, in a VQFN-24-EP(5x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN2 power_in Input supply to regulator with 3V to 36V operating range, requires high quality bypass capacitor to PGND2 with low impedance connection.
2 BOOT2 passive Bootstrap capacitor supply for channel 2 high-side gate driver, charged through internal diode from SW2 when low.
3 SW2 output Channel 2 switching node internally connected to high-side NMOS source and low-side NMOS drain, connects to power inductor.
4 PGND3 power_in Power return for internal low-side MOSFET with low impedance connection required to PGND1, PGND2, and exposed pad.
5 SW1 output Channel 1 switching node internally connected to high-side NMOS source and low-side NMOS drain, connects to power inductor.
6 BOOT1 passive Bootstrap capacitor supply for channel 1 high-side gate driver, charged through internal diode from SW1 when low.
7 VIN1 power_in Input supply to regulator with 3V to 36V operating range, requires high quality bypass capacitor to PGND1 with low impedance connection.
8 SERIES CAP1 passive Mid-point connection of series bypass capacitors between VIN1 and PGND1, can be left floating or connected to additional series capacitors.
9 PGND1 power_in Power return for internal low-side MOSFET with low impedance connection required to PGND2, PGND3, and bypass capacitors to VIN1.
10 SYNC input Synchronization and mode selection input: connect to AGND for auto/PFM mode or to VCC for FPWM mode, accepts external clock 200kHz to 2.2MHz.
11 PG1/MODE output Open-drain power-good flag for channel 1 in dual output mode; mode selection pin for secondary device in single output configuration.
12 EN1 input Active high enable input with 1.375V rising threshold that enables output 1 switching in dual mode or all phases in single mode.
13 BIAS & VOSNS1 input Output voltage sense and internal LDO bias input from non-switching inductor side, typical 3.3V to 5V with optional 0.1μF bypass capacitor.
14 FB1 input Feedback input to channel 1 error amplifier with 0.8V regulation threshold, sets output voltage 0.8V to 20V via resistive divider.
15 VCC power_out Internal LDO regulated output 3.1V to 3.7V supplying control circuits, requires 1μF bypass capacitor to AGND.
16 AGND power_in Analog ground reference for internal voltage reference, error amplifier, and feedback network circuits.
17 RT input Frequency programming input with resistor to AGND setting switching frequency from 100kHz to 2.2MHz range.
18 FB2/SS input Feedback input for channel 2 in dual output mode; soft-start capacitor input for external current limiting in single output mode.
19 VOSNS2/COMP input Output voltage sense for channel 2 fixed configurations in dual output mode; error amplifier output requiring RC compensation in single output mode.
20 EN2 input Active high enable input with 1.375V rising threshold that controls output 2 switching in dual mode or secondary phases in single mode.
21 CONFIG input Configuration pin with resistor to AGND selecting dual/single output mode, phase count (2/4/6), and spread spectrum modulation enable.
22 PG2/SYNCOUT output Open-drain power-good flag for channel 2 in dual output mode; phase-shifted synchronization clock output to secondary devices in single output mode.
23 PGND2 power_in Power return for internal low-side MOSFET with low impedance connection required to PGND1, PGND3, and bypass capacitors to VIN2.
24 SERIES CAP2 passive Mid-point connection of series bypass capacitors between VIN2 and PGND2, can be left floating for better pin FMEA.
25 PGND4 power_in Power return and thermal heat sink connection point requiring direct solder to system ground plane for thermal and mechanical performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(5x4)
Category Power Management (PMIC)
Pins 25

CAD (KiCad official)

  • Symbol: LMQ644A2QRXARQ1
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: VQFN-24-EP(5x4) (KiCad packages3D, STEP)
  • 3D model files: lmq644a2qrxarq1-etched.step / lmq644a2qrxarq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmq644a2qrxarq1.step / lmq644a2qrxarq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (64 pp, sha256 cff23df7edb8e196, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF