LMK5C33216RGCR

{
  "slug": "lmk5c33216rgcr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Jitter Attenuators, VQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "clock-timing",
    "lmk5c33216rgcr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "lmk5c33216rgcr.kicad_sym",
    "lmk5c33216rgcr.kicad_mod",
    "lmk5c33216rgcr.glb",
    "lmk5c33216rgcr.step",
    "lmk5c33216rgcr.lbr",
    "docs/hero.png",
    "docs/lmk5c33216rgcr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "lmk5c33216rgcr-hero.glb",
    "lmk5c33216rgcr-hero.overlay.json"
  ],
  "component": {
    "mpn": "LMK5C33216RGCR",
    "manufacturer": "Texas Instruments",
    "package": "VQFN-64(9x9)",
    "pin_count": 65,
    "category": "Clock/Timing",
    "subcategory": "Jitter Attenuators",
    "datasheet": "https://www.ti.com/cn/lit/gpn/lmk5c33216",
    "parts": {
      "symbol": "lmk5c33216rgcr.kicad_sym",
      "footprint": "lmk5c33216rgcr.kicad_mod",
      "model_3d": "lmk5c33216rgcr-hero.glb",
      "model_3d_plain": "lmk5c33216rgcr.glb",
      "model_3d_step": "lmk5c33216rgcr-etched.step",
      "model_3d_step_plain": "lmk5c33216rgcr.step",
      "lbr": "lmk5c33216rgcr.lbr"
    },
    "distributor_links": {
      "lcsc": "C3612930",
      "digikey": "296-LMK5C33216RGCRTR-ND",
      "mouser": "595-LMK5C33216RGCR"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T03:45:42Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-LMK5C33216RGCRTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-LMK5C33216RGCR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDDO_0_1",
        "type": "power_in",
        "description": "Power supply for OUT0 and OUT1; output supply range is 3.135 V to 3.465 V (3.3 V nominal) per Recommended Operating Conditions."
      },
      {
        "number": "2",
        "name": "OUT0_P",
        "type": "output",
        "description": "Clock Output 0 (true), sourced from all DPLL references, XO and all VCO post-dividers, with SYSREF output support and programmable LVPECL, LVDS, HSDS, 1.8-V LVCMOS or 2.65-V LVCMOS formats."
      },
      {
        "number": "3",
        "name": "OUT0_N",
        "type": "output",
        "description": "Clock Output 0 (complement), sourced from all DPLL references, XO and all VCO post-dividers, with SYSREF output support and programmable LVPECL, LVDS, HSDS, 1.8-V LVCMOS or 2.65-V LVCMOS formats."
      },
      {
        "number": "4",
        "name": "OUT1_N",
        "type": "output",
        "description": "Clock Output 1 (complement), sourced from all DPLL references, XO and all VCO post-dividers, with SYSREF output support and programmable LVPECL, LVDS, HSDS, 1.8-V LVCMOS or 2.65-V LVCMOS formats."
      },
      {
        "number": "5",
        "name": "OUT1_P",
        "type": "output",
        "description": "Clock Output 1 (true), sourced from all DPLL references, XO and all VCO post-dividers, with SYSREF output support and programmable LVPECL, LVDS, HSDS, 1.8-V LVCMOS or 2.65-V LVCMOS formats."
      },
      {
        "number": "6",
        "name": "LF1",
        "type": "passive",
        "description": "External loop filter capacitor for APLL1 (100 nF)."
      },
      {
        "number": "7",
        "name": "CAP_APLL1",
        "type": "passive",
        "description": "LDO bypass capacitor for APLL1 VCO (10 µF)."
      },
      {
        "number": "8",
        "name": "VDD_APLL1_XO",
        "type": "power_in",
        "description": "Power supply for XO and APLL1; core supply range is 3.135 V to 3.465 V (3.3 V nominal)."
      },
      {
        "number": "9",
        "name": "XO",
        "type": "input",
        "description": "XO/TCXO/OCXO reference input pin; the device requires a single XO/TCXO/OCXO and accepts 3.3-V LVCMOS drive directly."
      },
      {
        "number": "10",
        "name": "GPIO2",
        "type": "bidirectional",
        "description": "Power-on reset: ROM page select (GPIO2 input selects ROM to load as VCC, GND or float); in normal operation it is a programmable GPIO input or output."
      },
      {
        "number": "11",
        "name": "VDDO_2_3",
        "type": "power_in",
        "description": "Power supply for OUT2 and OUT3; output supply range is 3.135 V to 3.465 V (3.3 V nominal) per Recommended Operating Conditions."
      },
      {
        "number": "12",
        "name": "OUT2_P",
        "type": "output",
        "description": "Clock Output 2 (true), sourced from VCO1 and VCO2, with programmable LVPECL, LVDS or HSDS formats and no SYSREF output."
      },
      {
        "number": "13",
        "name": "OUT2_N",
        "type": "output",
        "description": "Clock Output 2 (complement), sourced from VCO1 and VCO2, with programmable LVPECL, LVDS or HSDS formats and no SYSREF output."
      },
      {
        "number": "14",
        "name": "OUT3_N",
        "type": "output",
        "description": "Clock Output 3 (complement), sourced from VCO1 and VCO2, with programmable LVPECL, LVDS or HSDS formats and no SYSREF output."
      },
      {
        "number": "15",
        "name": "OUT3_P",
        "type": "output",
        "description": "Clock Output 3 (true), sourced from VCO1 and VCO2, with programmable LVPECL, LVDS or HSDS formats and no SYSREF output."
      },
      {
        "number": "16",
        "name": "SDIO",
        "type": "bidirectional",
        "description": "SPI or I2C data pin (SDA); has a 670-kΩ pullup to the internal 2.6-V LDO."
      },
      {
        "number": "17",
        "name": "SCK",
        "type": "input",
        "description": "SPI or I2C clock pin (SCL); has a 670-kΩ pullup to the internal 2.6-V LDO."
      },
      {
        "number": "18",
        "name": "SCS_ADD",
        "type": "input",
        "description": "SPI chip select (2-state) during operation, and at power-on reset selects the I2C address LSB (3-state); has a 670-kΩ pullup to the internal 2.6-V LDO."
      },
      {
        "number": "19",
        "name": "LF2",
        "type": "passive",
        "description": "External loop filter capacitor for APLL2 (100 nF); input filters are recommended on SPI to prevent cross-contamination to the APLL2 VCO through this pin."
      },
      {
        "number": "20",
        "name": "CAP3_APLL2",
        "type": "passive",
        "description": "Internal bias bypass capacitor for APLL2 VCO (10 µF)."
      },
      {
        "number": "21",
        "name": "CAP2_APLL2",
        "type": "passive",
        "description": "Internal bias bypass capacitor for APLL2 VCO (10 µF)."
      },
      {
        "number": "22",
        "name": "CAP1_APLL2",
        "type": "passive",
        "description": "LDO bypass capacitor for APLL2 VCO (10 µF)."
      },
      {
        "number": "23",
        "name": "VDD_APLL2",
        "type": "power_in",
        "description": "Power supply for APLL2; core supply range is 3.135 V to 3.465 V (3.3 V nominal)."
      },
      {
        "number": "24",
        "name": "OUT5_P",
        "type": "output",
        "description": "Clock Output 5 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "25",
        "name": "OUT5_N",
        "type": "output",
        "description": "Clock Output 5 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "26",
        "name": "OUT4_N",
        "type": "output",
        "description": "Clock Output 4 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS, HSDS or CML formats; high-frequency output with channel divider bypass in open-collector CML format."
      },
      {
        "number": "27",
        "name": "OUT4_P",
        "type": "output",
        "description": "Clock Output 4 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS, HSDS or CML formats; high-frequency output with channel divider bypass in open-collector CML format."
      },
      {
        "number": "28",
        "name": "VDDO_4_TO_7",
        "type": "power_in",
        "description": "Power supply for OUT4 to OUT7; output supply range is 3.135 V to 3.465 V (3.3 V nominal) per Recommended Operating Conditions."
      },
      {
        "number": "29",
        "name": "OUT6_P",
        "type": "output",
        "description": "Clock Output 6 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS, HSDS or CML formats; high-frequency output with channel divider bypass in open-collector CML format."
      },
      {
        "number": "30",
        "name": "OUT6_N",
        "type": "output",
        "description": "Clock Output 6 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS, HSDS or CML formats; high-frequency output with channel divider bypass in open-collector CML format."
      },
      {
        "number": "31",
        "name": "OUT7_N",
        "type": "output",
        "description": "Clock Output 7 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "32",
        "name": "OUT7_P",
        "type": "output",
        "description": "Clock Output 7 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "33",
        "name": "VDD_IN0",
        "type": "power_in",
        "description": "Power supply for the IN0 DPLL reference input; core supply range is 3.135 V to 3.465 V (3.3 V nominal)."
      },
      {
        "number": "34",
        "name": "IN0_P",
        "type": "input",
        "description": "DPLL reference or buffered clock input to OUT0/OUT1 (true); accepts DC or AC-coupled inputs, input range 1 Hz to 800 MHz differential."
      },
      {
        "number": "35",
        "name": "IN0_N",
        "type": "input",
        "description": "DPLL reference or buffered clock input to OUT0/OUT1 (complement); accepts DC or AC-coupled inputs, input range 1 Hz to 800 MHz differential."
      },
      {
        "number": "36",
        "name": "PD#",
        "type": "input",
        "description": "Device power-down input, active low, with an internal 200-kΩ pullup to VCC."
      },
      {
        "number": "37",
        "name": "VDD_IN1",
        "type": "power_in",
        "description": "Power supply for the IN1 input port; core supply range is 3.135 V to 3.465 V (3.3 V nominal)."
      },
      {
        "number": "38",
        "name": "IN1_N",
        "type": "input",
        "description": "DPLL reference or buffered clock input to OUT0/OUT1 (complement); accepts DC or AC-coupled inputs, input range 1 Hz to 800 MHz differential."
      },
      {
        "number": "39",
        "name": "IN1_P",
        "type": "input",
        "description": "DPLL reference or buffered clock input to OUT0/OUT1 (true); accepts DC or AC-coupled inputs, input range 1 Hz to 800 MHz differential."
      },
      {
        "number": "40",
        "name": "CAP_DIG",
        "type": "passive",
        "description": "LDO bypass capacitor for the digital core logic (100 nF)."
      },
      {
        "number": "41",
        "name": "VDD_DIG",
        "type": "power_in",
        "description": "Power supply for the digital core; core supply range is 3.135 V to 3.465 V (3.3 V nominal)."
      },
      {
        "number": "42",
        "name": "OUT14_P",
        "type": "output",
        "description": "Clock Output 14 (true), sourced from VCO1, VCO2 and VCO3, with programmable LVPECL, LVDS or HSDS formats and no SYSREF output."
      },
      {
        "number": "43",
        "name": "OUT14_N",
        "type": "output",
        "description": "Clock Output 14 (complement), sourced from VCO1, VCO2 and VCO3, with programmable LVPECL, LVDS or HSDS formats and no SYSREF output."
      },
      {
        "number": "44",
        "name": "VDDO_14_15",
        "type": "power_in",
        "description": "Power supply for OUT14 and OUT15; output supply range is 3.135 V to 3.465 V (3.3 V nominal) per Recommended Operating Conditions."
      },
      {
        "number": "45",
        "name": "OUT15_N",
        "type": "output",
        "description": "Clock Output 15 (complement), sourced from VCO1, VCO2 and VCO3, with programmable LVPECL, LVDS or HSDS formats and no SYSREF output."
      },
      {
        "number": "46",
        "name": "OUT15_P",
        "type": "output",
        "description": "Clock Output 15 (true), sourced from VCO1, VCO2 and VCO3, with programmable LVPECL, LVDS or HSDS formats and no SYSREF output."
      },
      {
        "number": "47",
        "name": "VDD_APLL3",
        "type": "power_in",
        "description": "Power supply for APLL3; core supply range is 3.135 V to 3.465 V (3.3 V nominal)."
      },
      {
        "number": "48",
        "name": "CAP_APLL3",
        "type": "passive",
        "description": "Internal bias bypass capacitor for APLL3 (10 µF)."
      },
      {
        "number": "49",
        "name": "LF3",
        "type": "passive",
        "description": "External loop filter capacitor for APLL3 (470 nF)."
      },
      {
        "number": "50",
        "name": "GPIO0",
        "type": "bidirectional",
        "description": "Power-on reset: ROM page select (GPIO0 input selects ROM to load as VCC, GND or float); in normal operation it is a programmable GPIO input or output."
      },
      {
        "number": "51",
        "name": "OUT8_P",
        "type": "output",
        "description": "Clock Output 8 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "52",
        "name": "OUT8_N",
        "type": "output",
        "description": "Clock Output 8 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "53",
        "name": "OUT9_N",
        "type": "output",
        "description": "Clock Output 9 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "54",
        "name": "OUT9_P",
        "type": "output",
        "description": "Clock Output 9 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "55",
        "name": "VDDO_8_TO_13",
        "type": "power_in",
        "description": "Power supply for OUT8 to OUT13; output supply range is 3.135 V to 3.465 V (3.3 V nominal) per Recommended Operating Conditions."
      },
      {
        "number": "56",
        "name": "OUT10_P",
        "type": "output",
        "description": "Clock Output 10 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "57",
        "name": "OUT10_N",
        "type": "output",
        "description": "Clock Output 10 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "58",
        "name": "OUT11_N",
        "type": "output",
        "description": "Clock Output 11 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "59",
        "name": "OUT11_P",
        "type": "output",
        "description": "Clock Output 11 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "60",
        "name": "OUT12_P",
        "type": "output",
        "description": "Clock Output 12 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "61",
        "name": "OUT12_N",
        "type": "output",
        "description": "Clock Output 12 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "62",
        "name": "OUT13_N",
        "type": "output",
        "description": "Clock Output 13 (complement), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "63",
        "name": "OUT13_P",
        "type": "output",
        "description": "Clock Output 13 (true), sourced from VCO2 and VCO3, with SYSREF output support and programmable LVPECL, LVDS or HSDS formats."
      },
      {
        "number": "64",
        "name": "GPIO1",
        "type": "bidirectional",
        "description": "Power-on reset: selects I2C (GND) or SPI (VCC) communication mode; in normal operation it is a programmable GPIO input or output."
      },
      {
        "number": "65",
        "name": "DAP",
        "type": "power_in",
        "description": "Exposed die attach pad (thermal/ground pad) that is tied to ground."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin table (page 3) lists the DAP as N/A with no number. Pad number 65 is taken from the 'GND (DA; The datasheet gives a single supply range for all VDD and VDDO pins (3.135 V to 3.465 V). The per-pi; Descriptions for XO and IN0/IN1 combine the pin table with the features and schematic notes; the pin"
        ],
        "pages_sent": 12,
        "cost_usd": 0.1468,
        "at": "2026-10-08T03:45:22"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/lmk5c33216",
        "pages": 95,
        "sha256": "0ae72e15de5874ae",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 65,
        "described": 65,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9.0,
          9.0,
          0.75
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "lmk5c33216rgcr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9.0,
          9.0,
          0.75
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "5cdb08511497359ad0ec8029333fd08b2f0f5d556023fa6338539c357af7a65a",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}