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LMK1D2106RHAR

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Texas Instruments Clock Buffers, Drivers, Distributors, VQFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LMK1D2106RHAR

Texas Instruments · Clock Buffers, Drivers, Distributors · VQFN-40(6x6)

LMK1D2106RHAR from Texas Instruments, in a VQFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Output bank enable: left open enables both output groups, logic 0 disables both, and logic 1 disables one group while enabling the other; it has an internal 500-kΩ pullup and 320-kΩ pulldown.
2 IN1_P input Secondary clock input, positive leg, accepting differential or single-ended signals; when driven single-ended, the unused negative input must be biased per the datasheet figure 8-6.
3 IN1_N input Secondary clock input, negative leg, accepting differential or single-ended signals; when driven single-ended, this pin must be biased to an appropriate voltage per figure 8-6.
4 VAC_REF1 output Bias voltage output for capacitively coupled inputs on the secondary input; TI recommends a 0.1-µF capacitor to GND if used.
5 VDDB power_in Bank 1 supply voltage, 1.8 V, 2.5 V, or 3.3 V.
6 VDDA power_in Bank 0 supply voltage, 1.8 V, 2.5 V, or 3.3 V.
7 VAC_REF0 output Bias voltage output for capacitively coupled inputs on the primary input; TI recommends a 0.1-µF capacitor to GND if used.
8 IN0_P input Primary clock input, positive leg, accepting differential or single-ended signals; the unused negative input must be biased when driven single-ended.
9 IN0_N input Primary clock input, negative leg, accepting differential or single-ended signals; biased per figure 8-6 when driven single-ended.
10 AMP_SEL input Output amplitude select, with internal 500-kΩ pullup and 320-kΩ pulldown; selects the LVDS swing per datasheet table 8-3.
11 VDDA power_in Bank 0 supply voltage, 1.8 V, 2.5 V, or 3.3 V.
12 OUT0_P output Positive leg of differential LVDS output pair 0, designed to drive 50-Ω transmission lines.
13 OUT0_N output Negative leg of differential LVDS output pair 0, designed to drive 50-Ω transmission lines.
14 OUT1_P output Positive leg of differential LVDS output pair 1, designed to drive 50-Ω transmission lines.
15 OUT1_N output Negative leg of differential LVDS output pair 1, designed to drive 50-Ω transmission lines.
16 OUT2_P output Positive leg of differential LVDS output pair 2, designed to drive 50-Ω transmission lines.
17 OUT2_N output Negative leg of differential LVDS output pair 2, designed to drive 50-Ω transmission lines.
18 OUT3_P output Positive leg of differential LVDS output pair 3, designed to drive 50-Ω transmission lines.
19 OUT3_N output Negative leg of differential LVDS output pair 3, designed to drive 50-Ω transmission lines.
20 VDDA power_in Bank 0 supply voltage, 1.8 V, 2.5 V, or 3.3 V.
21 GND power_in Ground connection.
22 OUT4_P output Positive leg of differential LVDS output pair 4, designed to drive 50-Ω transmission lines.
23 OUT4_N output Negative leg of differential LVDS output pair 4, designed to drive 50-Ω transmission lines.
24 OUT5_P output Positive leg of differential LVDS output pair 5, designed to drive 50-Ω transmission lines.
25 OUT5_N output Negative leg of differential LVDS output pair 5, designed to drive 50-Ω transmission lines.
26 OUT6_P output Positive leg of differential LVDS output pair 6, designed to drive 50-Ω transmission lines.
27 OUT6_N output Negative leg of differential LVDS output pair 6, designed to drive 50-Ω transmission lines.
28 OUT7_P output Positive leg of differential LVDS output pair 7, designed to drive 50-Ω transmission lines.
29 OUT7_N output Negative leg of differential LVDS output pair 7, designed to drive 50-Ω transmission lines.
30 GND power_in Ground connection.
31 VDDB power_in Bank 1 supply voltage, 1.8 V, 2.5 V, or 3.3 V.
32 OUT8_P output Positive leg of differential LVDS output pair 8, designed to drive 50-Ω transmission lines.
33 OUT8_N output Negative leg of differential LVDS output pair 8, designed to drive 50-Ω transmission lines.
34 OUT9_P output Positive leg of differential LVDS output pair 9, designed to drive 50-Ω transmission lines.
35 OUT9_N output Negative leg of differential LVDS output pair 9, designed to drive 50-Ω transmission lines.
36 OUT10_P output Positive leg of differential LVDS output pair 10, designed to drive 50-Ω transmission lines.
37 OUT10_N output Negative leg of differential LVDS output pair 10, designed to drive 50-Ω transmission lines.
38 OUT11_P output Positive leg of differential LVDS output pair 11, designed to drive 50-Ω transmission lines.
39 OUT11_N output Negative leg of differential LVDS output pair 11, designed to drive 50-Ω transmission lines.
40 VDDB power_in Bank 1 supply voltage, 1.8 V, 2.5 V, or 3.3 V.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40(6x6)
Category Clock/Timing
Pins 41

CAD (KiCad official)

  • Symbol: LMK1D2106RHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: lmk1d2106rhar-etched.step / lmk1d2106rhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk1d2106rhar.step / lmk1d2106rhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (43 pp, sha256 5faeb5c6531c9194, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF