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LMK1D1208PRHAR

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Texas Instruments Clock Buffers, Drivers, Distributors, VQFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LMK1D1208PRHAR

Texas Instruments · Clock Buffers, Drivers, Distributors · VQFN-40(6x6)

LMK1D1208PRHAR from Texas Instruments, in a VQFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN_SEL input Input select with an internal 500-kΩ pullup and 320-kΩ pulldown that selects which clock input (IN0 or IN1) is sent to the outputs (see Table 9-2).
2 IN1_P input Secondary clock input, positive side of the differential pair or single-ended input; accepts LVDS, LVPECL, LVCMOS, HCSL or CML.
3 IN1_N input Secondary clock input, negative side of the differential pair; when driving single-ended, an appropriate bias voltage must be applied to this unused pin.
4 VAC_REF0 output Bias voltage output for capacitively coupled inputs; if used, TI recommends a 0.1-µF capacitor to GND on this pin.
5 OE7 input Output enable for channel 7: HIGH (default) enables OUT7; LOW disables OUT7 into Hi-Z state.
6 OE0 input Output enable for channel 0: HIGH (default) enables OUT0; LOW disables OUT0 into Hi-Z state.
7 VAC_REF1 output Bias voltage output for capacitively coupled inputs; if used, TI recommends a 0.1-µF capacitor to GND on this pin.
8 IN0_P input Primary clock input, positive side of the differential pair or single-ended input; accepts LVDS, LVPECL, LVCMOS, HCSL or CML.
9 IN0_N input Primary clock input, negative side of the differential pair; when driving single-ended, an appropriate bias voltage must be applied to this unused pin.
10 AMP_SEL input Output amplitude swing select with an internal 500-kΩ pullup and 320-kΩ pulldown (see Table 9-4).
11 VDD power_in Device power supply, 1.8 V, 2.5 V or 3.3 V (supply range 1.71-1.89 V, 2.375-2.625 V, or 3.135-3.465 V).
12 OUT0_P output Differential LVDS output pair 0, positive side.
13 OUT0_N output Differential LVDS output pair 0, negative side.
14 OUT1_P output Differential LVDS output pair 1, positive side.
15 OUT1_N output Differential LVDS output pair 1, negative side.
16 OE1 input Output enable for channel 1: HIGH (default) enables OUT1; LOW disables OUT1 into Hi-Z state.
17 OE2 input Output enable for channel 2: HIGH (default) enables OUT2; LOW disables OUT2 into Hi-Z state.
18 OE3 input Output enable for channel 3: HIGH (default) enables OUT3; LOW disables OUT3 into Hi-Z state.
19 NC unconnected No connection; leave floating.
20 VDD power_in Device power supply, 1.8 V, 2.5 V or 3.3 V (supply range 1.71-1.89 V, 2.375-2.625 V, or 3.135-3.465 V).
21 GND power_in Ground.
22 OUT2_P output Differential LVDS output pair 2, positive side.
23 OUT2_N output Differential LVDS output pair 2, negative side.
24 OUT3_P output Differential LVDS output pair 3, positive side.
25 OUT3_N output Differential LVDS output pair 3, negative side.
26 OUT4_P output Differential LVDS output pair 4, positive side.
27 OUT4_N output Differential LVDS output pair 4, negative side.
28 OUT5_P output Differential LVDS output pair 5, positive side.
29 OUT5_N output Differential LVDS output pair 5, negative side.
30 GND power_in Ground.
31 VDD power_in Device power supply, 1.8 V, 2.5 V or 3.3 V (supply range 1.71-1.89 V, 2.375-2.625 V, or 3.135-3.465 V).
32 NC unconnected No connection; leave floating.
33 OE4 input Output enable for channel 4: HIGH (default) enables OUT4; LOW disables OUT4 into Hi-Z state.
34 OE5 input Output enable for channel 5: HIGH (default) enables OUT5; LOW disables OUT5 into Hi-Z state.
35 OE6 input Output enable for channel 6: HIGH (default) enables OUT6; LOW disables OUT6 into Hi-Z state.
36 OUT6_P output Differential LVDS output pair 6, positive side.
37 OUT6_N output Differential LVDS output pair 6, negative side.
38 OUT7_P output Differential LVDS output pair 7, positive side.
39 OUT7_N output Differential LVDS output pair 7, negative side.
40 VDD power_in Device power supply, 1.8 V, 2.5 V or 3.3 V (supply range 1.71-1.89 V, 2.375-2.625 V, or 3.135-3.465 V).
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40(6x6)
Category Clock/Timing
Pins 41

CAD (KiCad official)

  • Symbol: LMK1D1208PRHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: lmk1d1208prhar-etched.step / lmk1d1208prhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk1d1208prhar.step / lmk1d1208prhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 6971e5b101c5e8f8, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF