component
LMK04832NKDT
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Texas Instruments Jitter Attenuators, WQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+102@@ -0,0 +1,102 @@+# LMK04832NKDT++**Texas Instruments** · Jitter Attenuators · WQFN-64(9x9)++LMK04832NKDT from Texas Instruments, in a WQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLKout0 | output | Programmable Clock output 0 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock. |+| 2 | CLKout0* | output | Differential complement of CLKout0 with selectable formats CML, LVPECL, LCPECL, or LVDS. |+| 3 | CLKout1 | output | Programmable Clock output 1 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock. |+| 4 | CLKout1* | output | Differential complement of CLKout1 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. |+| 5 | RESET/GPO | input | CMOS Device reset input or General Purpose Output. |+| 6 | SYNC/SYSREF_REQ | input | CMOS Synchronization input or SYSREF_REQ for requesting continuous SYSREF. |+| 7 | NC | unconnected | Do not connect. |+| 8 | NC | unconnected | Do not connect. |+| 9 | NC | unconnected | Do not connect. |+| 10 | Vcc1_VCO | power_in | Power supply for VCO and clock distribution. |+| 11 | LDObyp1 | passive | LDO Bypass capacitor connection; bypass to ground with 10-µF capacitor. |+| 12 | LDObyp2 | passive | LDO Bypass capacitor connection; bypass to ground with 0.1-µF capacitor. |+| 13 | CLKout3 | output | Programmable Clock output 3 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock. |+| 14 | CLKout3* | output | Differential complement of CLKout3 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. |+| 15 | CLKout2 | output | Programmable Clock output 2 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock. |+| 16 | CLKout2* | output | Differential complement of CLKout2 with selectable formats CML, LVPECL, LCPECL, or LVDS. |+| 17 | Vcc2_CG1 | power_in | Power supply for clock outputs 2 and 3. |+| 18 | CS* | input | CMOS Chip Select active low for SPI interface. |+| 19 | SCK | input | CMOS SPI Clock input. |+| 20 | SDIO | bidirectional | CMOS SPI Data input/output. |+| 21 | Vcc3_SYSREF | power_in | Power supply for SYSREF divider and SYNC. |+| 22 | CLKout5 | output | Programmable Clock output 5 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock. |+| 23 | CLKout5* | output | Differential complement of CLKout5 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. |+| 24 | CLKout4 | output | Programmable Clock output 4 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock. |+| 25 | CLKout4* | output | Differential complement of CLKout4 with selectable formats CML, LVPECL, LCPECL, or LVDS. |+| 26 | Vcc4_CG2 | power_in | Power supply for clock outputs 4, 5, 6, and 7. |+| 27 | CLKout6 | output | Programmable Clock output 6 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock. |+| 28 | CLKout6* | output | Differential complement of CLKout6 with selectable formats CML, LVPECL, LCPECL, or LVDS. |+| 29 | CLKout7 | output | Programmable Clock output 7 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock. |+| 30 | CLKout7* | output | Differential complement of CLKout7 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. |+| 31 | Status_LD1 | bidirectional | Programmable status output or general purpose I/O pin. |+| 32 | CPout1 | output | Charge pump 1 analog output; place resistor and capacitor close to IC. |+| 33 | Vcc5_DIG | power_in | Power supply for digital circuitry. |+| 34 | CLKin1 | input | Reference Clock Input Port 1 for PLL1; also serves as feedback input for 0-delay mode or Fin1 for external VCO/clock distribution input. |+| 35 | CLKin1* | input | Differential complement of CLKin1 for PLL1; also serves as feedback or Fin1 complement input. |+| 36 | Vcc6_PLL1 | power_in | Power supply for PLL1, charge pump 1, and holdover DAC. |+| 37 | CLKin0 | input | Reference Clock Input Port 0 for PLL1 with differential termination. |+| 38 | CLKin0* | input | Differential complement of CLKin0 for PLL1. |+| 39 | Vcc7_OSCout | power_in | Power supply for OSCout output port. |+| 40 | OSCout | bidirectional | Programmable buffered output of OSCin or reference input port CLKin2 with AC coupling. |+| 41 | OSCout* | bidirectional | Differential complement of OSCout for buffered output or CLKin2 complement input. |+| 42 | Vcc8_OSCin | power_in | Power supply for OSCin. |+| 43 | OSCin | input | Feedback to PLL1 and reference input to PLL2; AC-coupled feedback input. |+| 44 | OSCin* | input | Differential complement of OSCin for AC-coupled feedback to PLL1 and reference to PLL2. |+| 45 | Vcc9_CP2 | power_in | Power supply for PLL2 Charge Pump. |+| 46 | CPout2 | output | Charge pump 2 analog output; place resistor and capacitor close to IC. |+| 47 | Vcc10_PLL2 | power_in | Power supply for PLL2. |+| 48 | Status_LD2 | bidirectional | Programmable status output or general purpose I/O pin. |+| 49 | CLKout9 | output | Programmable Clock output 9 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock. |+| 50 | CLKout9* | output | Differential complement of CLKout9 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. |+| 51 | CLKout8 | output | Programmable Clock output 8 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest Device Clock. |+| 52 | CLKout8* | output | Differential complement of CLKout8 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. |+| 53 | Vcc11_CG3 | power_in | Power supply for clock outputs 8, 9, 10, and 11. |+| 54 | CLKout10 | output | Programmable Clock output 10 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest Device Clock. |+| 55 | CLKout10* | output | Differential complement of CLKout10 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. |+| 56 | CLKout11 | output | Programmable Clock output 11 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock. |+| 57 | CLKout11* | output | Differential complement of CLKout11 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. |+| 58 | CLKin_SEL0 | bidirectional | Programmable clock input selection or general purpose I/O pin. |+| 59 | CLKin_SEL1 | bidirectional | Programmable clock input selection or general purpose I/O pin. |+| 60 | CLKout13 | output | Programmable Clock output 13 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock. |+| 61 | CLKout13* | output | Differential complement of CLKout13 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS. |+| 62 | CLKout12 | output | Programmable Clock output 12 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock. |+| 63 | CLKout12* | output | Differential complement of CLKout12 with selectable formats CML, LVPECL, LCPECL, or LVDS. |+| 64 | Vcc12_CG0 | power_in | Power supply for clock outputs 0, 1, 12, and 13. |+| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-64(9x9) |+| Category | Clock/Timing |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `LMK04832NKDT`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: WQFN-64(9x9) (KiCad packages3D, STEP)+- 3D model files: `lmk04832nkdt-etched.step` / `lmk04832nkdt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmk04832nkdt.step` / `lmk04832nkdt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmk04832) (107 pp, sha256 `ca59690a75ad12b5`, retrieved 2026-10-06, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lmk04832nkdt-datasheet.pdf)
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for JESD204B systems suggest Device Clock."+ },+ {+ "number": "2",+ "name": "CLKout0*",+ "type": "output",+ "description": "Differential complement of CLKout0 with selectable formats CML, LVPECL, LCPECL, or LVDS."+ },+ {+ "number": "3",+ "name": "CLKout1",+ "type": "output",+ "description": "Programmable Clock output 1 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock."+ },+ {+ "number": "4",+ "name": "CLKout1*",+ "type": "output",+ "description": "Differential complement of CLKout1 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS."+ },+ {+ "number": "5",+ "name": "RESET/GPO",+ "type": "input",+ "description": "CMOS Device reset input or General Purpose Output."+ },+ {+ "number": "6",+ "name": "SYNC/SYSREF_REQ",+ "type": "input",+ "description": "CMOS Synchronization input or SYSREF_REQ for requesting continuous SYSREF."+ },+ {+ "number": "7",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "8",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "9",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect."+ },+ {+ "number": "10",+ "name": "Vcc1_VCO",+ "type": "power_in",+ "description": "Power supply for VCO and clock distribution."+ },+ {+ "number": "11",+ "name": "LDObyp1",+ "type": "passive",+ "description": "LDO Bypass capacitor connection; bypass to ground with 10-µF capacitor."+ },+ {+ "number": "12",+ "name": "LDObyp2",+ "type": "passive",+ "description": "LDO Bypass capacitor connection; bypass to ground with 0.1-µF capacitor."+ },+ {+ "number": "13",+ "name": "CLKout3",+ "type": "output",+ "description": "Programmable Clock output 3 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock."+ },+ {+ "number": "14",+ "name": "CLKout3*",+ "type": "output",+ "description": "Differential complement of CLKout3 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS."+ },+ {+ "number": "15",+ "name": "CLKout2",+ "type": "output",+ "description": "Programmable Clock output 2 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock."+ },+ {+ "number": "16",+ "name": "CLKout2*",+ "type": "output",+ "description": "Differential complement of CLKout2 with selectable formats CML, LVPECL, LCPECL, or LVDS."+ },+ {+ "number": "17",+ "name": "Vcc2_CG1",+ "type": "power_in",+ "description": "Power supply for clock outputs 2 and 3."+ },+ {+ "number": "18",+ "name": "CS*",+ "type": "input",+ "description": "CMOS Chip Select active low for SPI interface."+ },+ {+ "number": "19",+ "name": "SCK",+ "type": "input",+ "description": "CMOS SPI Clock input."+ },+ {+ "number": "20",+ "name": "SDIO",+ "type": "bidirectional",+ "description": "CMOS SPI Data input/output."+ },+ {+ "number": "21",+ "name": "Vcc3_SYSREF",+ "type": "power_in",+ "description": "Power supply for SYSREF divider and SYNC."+ },+ {+ "number": "22",+ "name": "CLKout5",+ "type": "output",+ "description": "Programmable Clock output 5 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock."+ },+ {+ "number": "23",+ "name": "CLKout5*",+ "type": "output",+ "description": "Differential complement of CLKout5 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS."+ },+ {+ "number": "24",+ "name": "CLKout4",+ "type": "output",+ "description": "Programmable Clock output 4 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock."+ },+ {+ "number": "25",+ "name": "CLKout4*",+ "type": "output",+ "description": "Differential complement of CLKout4 with selectable formats CML, LVPECL, LCPECL, or LVDS."+ },+ {+ "number": "26",+ "name": "Vcc4_CG2",+ "type": "power_in",+ "description": "Power supply for clock outputs 4, 5, 6, and 7."+ },+ {+ "number": "27",+ "name": "CLKout6",+ "type": "output",+ "description": "Programmable Clock output 6 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock."+ },+ {+ "number": "28",+ "name": "CLKout6*",+ "type": "output",+ "description": "Differential complement of CLKout6 with selectable formats CML, LVPECL, LCPECL, or LVDS."+ },+ {+ "number": "29",+ "name": "CLKout7",+ "type": "output",+ "description": "Programmable Clock output 7 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock."+ },+ {+ "number": "30",+ "name": "CLKout7*",+ "type": "output",+ "description": "Differential complement of CLKout7 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS."+ },+ {+ "number": "31",+ "name": "Status_LD1",+ "type": "bidirectional",+ "description": "Programmable status output or general purpose I/O pin."+ },+ {+ "number": "32",+ "name": "CPout1",+ "type": "output",+ "description": "Charge pump 1 analog output; place resistor and capacitor close to IC."+ },+ {+ "number": "33",+ "name": "Vcc5_DIG",+ "type": "power_in",+ "description": "Power supply for digital circuitry."+ },+ {+ "number": "34",+ "name": "CLKin1",+ "type": "input",+ "description": "Reference Clock Input Port 1 for PLL1; also serves as feedback input for 0-delay mode or Fin1 for external VCO/clock distribution input."+ },+ {+ "number": "35",+ "name": "CLKin1*",+ "type": "input",+ "description": "Differential complement of CLKin1 for PLL1; also serves as feedback or Fin1 complement input."+ },+ {+ "number": "36",+ "name": "Vcc6_PLL1",+ "type": "power_in",+ "description": "Power supply for PLL1, charge pump 1, and holdover DAC."+ },+ {+ "number": "37",+ "name": "CLKin0",+ "type": "input",+ "description": "Reference Clock Input Port 0 for PLL1 with differential termination."+ },+ {+ "number": "38",+ "name": "CLKin0*",+ "type": "input",+ "description": "Differential complement of CLKin0 for PLL1."+ },+ {+ "number": "39",+ "name": "Vcc7_OSCout",+ "type": "power_in",+ "description": "Power supply for OSCout output port."+ },+ {+ "number": "40",+ "name": "OSCout",+ "type": "bidirectional",+ "description": "Programmable buffered output of OSCin or reference input port CLKin2 with AC coupling."+ },+ {+ "number": "41",+ "name": "OSCout*",+ "type": "bidirectional",+ "description": "Differential complement of OSCout for buffered output or CLKin2 complement input."+ },+ {+ "number": "42",+ "name": "Vcc8_OSCin",+ "type": "power_in",+ "description": "Power supply for OSCin."+ },+ {+ "number": "43",+ "name": "OSCin",+ "type": "input",+ "description": "Feedback to PLL1 and reference input to PLL2; AC-coupled feedback input."+ },+ {+ "number": "44",+ "name": "OSCin*",+ "type": "input",+ "description": "Differential complement of OSCin for AC-coupled feedback to PLL1 and reference to PLL2."+ },+ {+ "number": "45",+ "name": "Vcc9_CP2",+ "type": "power_in",+ "description": "Power supply for PLL2 Charge Pump."+ },+ {+ "number": "46",+ "name": "CPout2",+ "type": "output",+ "description": "Charge pump 2 analog output; place resistor and capacitor close to IC."+ },+ {+ "number": "47",+ "name": "Vcc10_PLL2",+ "type": "power_in",+ "description": "Power supply for PLL2."+ },+ {+ "number": "48",+ "name": "Status_LD2",+ "type": "bidirectional",+ "description": "Programmable status output or general purpose I/O pin."+ },+ {+ "number": "49",+ "name": "CLKout9",+ "type": "output",+ "description": "Programmable Clock output 9 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock."+ },+ {+ "number": "50",+ "name": "CLKout9*",+ "type": "output",+ "description": "Differential complement of CLKout9 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS."+ },+ {+ "number": "51",+ "name": "CLKout8",+ "type": "output",+ "description": "Programmable Clock output 8 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest Device Clock."+ },+ {+ "number": "52",+ "name": "CLKout8*",+ "type": "output",+ "description": "Differential complement of CLKout8 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS."+ },+ {+ "number": "53",+ "name": "Vcc11_CG3",+ "type": "power_in",+ "description": "Power supply for clock outputs 8, 9, 10, and 11."+ },+ {+ "number": "54",+ "name": "CLKout10",+ "type": "output",+ "description": "Programmable Clock output 10 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest Device Clock."+ },+ {+ "number": "55",+ "name": "CLKout10*",+ "type": "output",+ "description": "Differential complement of CLKout10 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS."+ },+ {+ "number": "56",+ "name": "CLKout11",+ "type": "output",+ "description": "Programmable Clock output 11 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock."+ },+ {+ "number": "57",+ "name": "CLKout11*",+ "type": "output",+ "description": "Differential complement of CLKout11 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS."+ },+ {+ "number": "58",+ "name": "CLKin_SEL0",+ "type": "bidirectional",+ "description": "Programmable clock input selection or general purpose I/O pin."+ },+ {+ "number": "59",+ "name": "CLKin_SEL1",+ "type": "bidirectional",+ "description": "Programmable clock input selection or general purpose I/O pin."+ },+ {+ "number": "60",+ "name": "CLKout13",+ "type": "output",+ "description": "Programmable Clock output 13 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock."+ },+ {+ "number": "61",+ "name": "CLKout13*",+ "type": "output",+ "description": "Differential complement of CLKout13 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS."+ },+ {+ "number": "62",+ "name": "CLKout12",+ "type": "output",+ "description": "Programmable Clock output 12 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock."+ },+ {+ "number": "63",+ "name": "CLKout12*",+ "type": "output",+ "description": "Differential complement of CLKout12 with selectable formats CML, LVPECL, LCPECL, or LVDS."+ },+ {+ "number": "64",+ "name": "Vcc12_CG0",+ "type": "power_in",+ "description": "Power supply for clock outputs 0, 1, 12, and 13."+ },+ {+ "number": "65",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: PIN 9 shown in package diagram as NC but not explicitly listed in pin function table; inferred as NC",+ "exposed pad 65 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 15,+ "cost_usd": 0.2286,+ "at": "2026-10-06T16:35:37"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lmk04832",+ "pages": 107,+ "sha256": "ca59690a75ad12b5",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}