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LMK04832NKDT

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Texas Instruments Jitter Attenuators, WQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LMK04832NKDT

Texas Instruments · Jitter Attenuators · WQFN-64(9x9)

LMK04832NKDT from Texas Instruments, in a WQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKout0 output Programmable Clock output 0 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock.
2 CLKout0* output Differential complement of CLKout0 with selectable formats CML, LVPECL, LCPECL, or LVDS.
3 CLKout1 output Programmable Clock output 1 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock.
4 CLKout1* output Differential complement of CLKout1 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.
5 RESET/GPO input CMOS Device reset input or General Purpose Output.
6 SYNC/SYSREF_REQ input CMOS Synchronization input or SYSREF_REQ for requesting continuous SYSREF.
7 NC unconnected Do not connect.
8 NC unconnected Do not connect.
9 NC unconnected Do not connect.
10 Vcc1_VCO power_in Power supply for VCO and clock distribution.
11 LDObyp1 passive LDO Bypass capacitor connection; bypass to ground with 10-µF capacitor.
12 LDObyp2 passive LDO Bypass capacitor connection; bypass to ground with 0.1-µF capacitor.
13 CLKout3 output Programmable Clock output 3 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock.
14 CLKout3* output Differential complement of CLKout3 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.
15 CLKout2 output Programmable Clock output 2 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock.
16 CLKout2* output Differential complement of CLKout2 with selectable formats CML, LVPECL, LCPECL, or LVDS.
17 Vcc2_CG1 power_in Power supply for clock outputs 2 and 3.
18 CS* input CMOS Chip Select active low for SPI interface.
19 SCK input CMOS SPI Clock input.
20 SDIO bidirectional CMOS SPI Data input/output.
21 Vcc3_SYSREF power_in Power supply for SYSREF divider and SYNC.
22 CLKout5 output Programmable Clock output 5 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock.
23 CLKout5* output Differential complement of CLKout5 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.
24 CLKout4 output Programmable Clock output 4 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock.
25 CLKout4* output Differential complement of CLKout4 with selectable formats CML, LVPECL, LCPECL, or LVDS.
26 Vcc4_CG2 power_in Power supply for clock outputs 4, 5, 6, and 7.
27 CLKout6 output Programmable Clock output 6 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock.
28 CLKout6* output Differential complement of CLKout6 with selectable formats CML, LVPECL, LCPECL, or LVDS.
29 CLKout7 output Programmable Clock output 7 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock.
30 CLKout7* output Differential complement of CLKout7 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.
31 Status_LD1 bidirectional Programmable status output or general purpose I/O pin.
32 CPout1 output Charge pump 1 analog output; place resistor and capacitor close to IC.
33 Vcc5_DIG power_in Power supply for digital circuitry.
34 CLKin1 input Reference Clock Input Port 1 for PLL1; also serves as feedback input for 0-delay mode or Fin1 for external VCO/clock distribution input.
35 CLKin1* input Differential complement of CLKin1 for PLL1; also serves as feedback or Fin1 complement input.
36 Vcc6_PLL1 power_in Power supply for PLL1, charge pump 1, and holdover DAC.
37 CLKin0 input Reference Clock Input Port 0 for PLL1 with differential termination.
38 CLKin0* input Differential complement of CLKin0 for PLL1.
39 Vcc7_OSCout power_in Power supply for OSCout output port.
40 OSCout bidirectional Programmable buffered output of OSCin or reference input port CLKin2 with AC coupling.
41 OSCout* bidirectional Differential complement of OSCout for buffered output or CLKin2 complement input.
42 Vcc8_OSCin power_in Power supply for OSCin.
43 OSCin input Feedback to PLL1 and reference input to PLL2; AC-coupled feedback input.
44 OSCin* input Differential complement of OSCin for AC-coupled feedback to PLL1 and reference to PLL2.
45 Vcc9_CP2 power_in Power supply for PLL2 Charge Pump.
46 CPout2 output Charge pump 2 analog output; place resistor and capacitor close to IC.
47 Vcc10_PLL2 power_in Power supply for PLL2.
48 Status_LD2 bidirectional Programmable status output or general purpose I/O pin.
49 CLKout9 output Programmable Clock output 9 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock.
50 CLKout9* output Differential complement of CLKout9 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.
51 CLKout8 output Programmable Clock output 8 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest Device Clock.
52 CLKout8* output Differential complement of CLKout8 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.
53 Vcc11_CG3 power_in Power supply for clock outputs 8, 9, 10, and 11.
54 CLKout10 output Programmable Clock output 10 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest Device Clock.
55 CLKout10* output Differential complement of CLKout10 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.
56 CLKout11 output Programmable Clock output 11 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock.
57 CLKout11* output Differential complement of CLKout11 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.
58 CLKin_SEL0 bidirectional Programmable clock input selection or general purpose I/O pin.
59 CLKin_SEL1 bidirectional Programmable clock input selection or general purpose I/O pin.
60 CLKout13 output Programmable Clock output 13 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS; for JESD204B systems suggest SYSREF Clock.
61 CLKout13* output Differential complement of CLKout13 with selectable formats CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.
62 CLKout12 output Programmable Clock output 12 with selectable formats CML, LVPECL, LCPECL, or LVDS; for JESD204B systems suggest Device Clock.
63 CLKout12* output Differential complement of CLKout12 with selectable formats CML, LVPECL, LCPECL, or LVDS.
64 Vcc12_CG0 power_in Power supply for clock outputs 0, 1, 12, and 13.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-64(9x9)
Category Clock/Timing
Pins 65

CAD (KiCad official)

  • Symbol: LMK04832NKDT
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: WQFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: lmk04832nkdt-etched.step / lmk04832nkdt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk04832nkdt.step / lmk04832nkdt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (107 pp, sha256 ca59690a75ad12b5, retrieved 2026-10-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF