LMK04828SNKDREP

{
  "slug": "lmk04828snkdrep",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "clock-timing",
    "lmk04828snkdrep",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "lmk04828snkdrep.kicad_sym",
    "lmk04828snkdrep.kicad_mod",
    "lmk04828snkdrep.glb",
    "lmk04828snkdrep.step",
    "lmk04828snkdrep.lbr",
    "docs/hero.png",
    "docs/lmk04828snkdrep-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "lmk04828snkdrep-hero.glb",
    "lmk04828snkdrep-hero.overlay.json"
  ],
  "component": {
    "mpn": "LMK04828SNKDREP",
    "manufacturer": "Texas Instruments",
    "package": "WQFN-64-EP(9x9)",
    "pin_count": 65,
    "category": "Clock/Timing",
    "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",
    "datasheet": "https://www.ti.com/cn/lit/gpn/lmk04828-ep",
    "parts": {
      "symbol": "lmk04828snkdrep.kicad_sym",
      "footprint": "lmk04828snkdrep.kicad_mod",
      "model_3d": "lmk04828snkdrep-hero.glb",
      "model_3d_plain": "lmk04828snkdrep.glb",
      "model_3d_step": "lmk04828snkdrep-etched.step",
      "model_3d_step_plain": "lmk04828snkdrep.step",
      "lbr": "lmk04828snkdrep.lbr"
    },
    "distributor_links": {
      "lcsc": "C2666373",
      "digikey": "LMK04828SNKDREP-ND",
      "mouser": "595-LMK04828SNKDREP"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T00:57:38Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "LMK04828SNKDREP-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-LMK04828SNKDREP",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "DCLKout0",
        "type": "output",
        "description": "Programmable device clock output 0 (true side of the differential pair; complement is pin 2)."
      },
      {
        "number": "2",
        "name": "DCLKout0*",
        "type": "output",
        "description": "Complementary side of programmable device clock output 0."
      },
      {
        "number": "3",
        "name": "SDCLKout1",
        "type": "output",
        "description": "Programmable SYSREF or device clock output 1 (true side)."
      },
      {
        "number": "4",
        "name": "SDCLKout1*",
        "type": "output",
        "description": "Complementary side of programmable SYSREF or device clock output 1."
      },
      {
        "number": "5",
        "name": "RESET/GPO",
        "type": "input",
        "description": "CMOS device reset input, or general-purpose output (GPO) when so programmed."
      },
      {
        "number": "6",
        "name": "SYNC/SYSREF_REQ",
        "type": "input",
        "description": "CMOS synchronization input, or SYSREF_REQ for requesting continuous SYSREF."
      },
      {
        "number": "7",
        "name": "NC",
        "type": "unconnected",
        "description": "Do not connect; this pin must be left floating."
      },
      {
        "number": "8",
        "name": "NC",
        "type": "unconnected",
        "description": "Do not connect; this pin must be left floating."
      },
      {
        "number": "9",
        "name": "NC",
        "type": "unconnected",
        "description": "Do not connect; this pin must be left floating."
      },
      {
        "number": "10",
        "name": "Vcc1_VCO",
        "type": "power_in",
        "description": "Power supply for the VCO LDO."
      },
      {
        "number": "11",
        "name": "LDObyp1",
        "type": "passive",
        "description": "Analog LDO bypass, bypassed to ground with a 10-µF capacitor."
      },
      {
        "number": "12",
        "name": "LDObyp2",
        "type": "passive",
        "description": "Analog LDO bypass, bypassed to ground with a 0.1-µF capacitor."
      },
      {
        "number": "13",
        "name": "SDCLKout3",
        "type": "output",
        "description": "Programmable SYSREF or device clock output 3 (true side)."
      },
      {
        "number": "14",
        "name": "SDCLKout3*",
        "type": "output",
        "description": "Complementary side of programmable SYSREF or device clock output 3."
      },
      {
        "number": "15",
        "name": "DCLKout2",
        "type": "output",
        "description": "Programmable device clock output 2 (true side)."
      },
      {
        "number": "16",
        "name": "DCLKout2*",
        "type": "output",
        "description": "Complementary side of programmable device clock output 2."
      },
      {
        "number": "17",
        "name": "Vcc2_CG1",
        "type": "power_in",
        "description": "Power supply for clock outputs 2 and 3."
      },
      {
        "number": "18",
        "name": "CS*",
        "type": "input",
        "description": "CMOS chip select for the SPI interface."
      },
      {
        "number": "19",
        "name": "SCK",
        "type": "input",
        "description": "CMOS SPI clock."
      },
      {
        "number": "20",
        "name": "SDIO",
        "type": "bidirectional",
        "description": "CMOS SPI data."
      },
      {
        "number": "21",
        "name": "Vcc3_SYSREF",
        "type": "power_in",
        "description": "Power supply for the SYSREF divider and SYNC."
      },
      {
        "number": "22",
        "name": "SDCLKout5",
        "type": "output",
        "description": "Programmable SYSREF or device clock output 5 (true side)."
      },
      {
        "number": "23",
        "name": "SDCLKout5*",
        "type": "output",
        "description": "Complementary side of programmable SYSREF or device clock output 5."
      },
      {
        "number": "24",
        "name": "DCLKout4",
        "type": "output",
        "description": "Programmable device clock output 4 (true side)."
      },
      {
        "number": "25",
        "name": "DCLKout4*",
        "type": "output",
        "description": "Complementary side of programmable device clock output 4."
      },
      {
        "number": "26",
        "name": "Vcc4_CG2",
        "type": "power_in",
        "description": "Power supply for clock outputs 4, 5, 6 and 7."
      },
      {
        "number": "27",
        "name": "DCLKout6",
        "type": "output",
        "description": "Programmable device clock output 6 (true side)."
      },
      {
        "number": "28",
        "name": "DCLKout6*",
        "type": "output",
        "description": "Complementary side of programmable device clock output 6."
      },
      {
        "number": "29",
        "name": "SDCLKout7",
        "type": "output",
        "description": "Programmable SYSREF or device clock output 7 (true side)."
      },
      {
        "number": "30",
        "name": "SDCLKout7*",
        "type": "output",
        "description": "Complementary side of programmable SYSREF or device clock output 7."
      },
      {
        "number": "31",
        "name": "Status_LD1",
        "type": "bidirectional",
        "description": "Programmable status pin."
      },
      {
        "number": "32",
        "name": "CPout1",
        "type": "output",
        "description": "Charge pump 1 output."
      },
      {
        "number": "33",
        "name": "Vcc5_DIG",
        "type": "power_in",
        "description": "Power supply for the digital circuitry."
      },
      {
        "number": "34",
        "name": "CLKin1/Fin/FBCLKin",
        "type": "input",
        "description": "Reference clock input port 1 for PLL1; the same pin also serves as FBCLKin (external feedback, 0-delay mode) or Fin (external VCO input, external VCO mode)."
      },
      {
        "number": "35",
        "name": "CLKin1*/Fin*/FBCLKin*",
        "type": "input",
        "description": "Complementary input for CLKin1, FBCLKin or Fin."
      },
      {
        "number": "36",
        "name": "Vcc6_PLL1",
        "type": "power_in",
        "description": "Power supply for PLL1, charge pump 1 and the holdover DAC."
      },
      {
        "number": "37",
        "name": "CLKin0",
        "type": "input",
        "description": "Reference clock input port 0 for PLL1 (true side)."
      },
      {
        "number": "38",
        "name": "CLKin0*",
        "type": "input",
        "description": "Complementary reference clock input port 0 for PLL1."
      },
      {
        "number": "39",
        "name": "Vcc7_OSCout",
        "type": "power_in",
        "description": "Power supply for the OSCout port."
      },
      {
        "number": "40",
        "name": "OSCout/CLKin2",
        "type": "bidirectional",
        "description": "Programmable buffered output of the OSCin port; the same pin can also serve as reference Input Port 2 (CLKin2) for PLL1."
      },
      {
        "number": "41",
        "name": "OSCout*/CLKin2*",
        "type": "bidirectional",
        "description": "Complementary programmable buffered OSCin output, or complementary CLKin2 reference input for PLL1."
      },
      {
        "number": "42",
        "name": "Vcc8_OSCin",
        "type": "power_in",
        "description": "Power supply for OSCin."
      },
      {
        "number": "43",
        "name": "OSCin",
        "type": "input",
        "description": "Feedback to PLL1 and reference input to PLL2; AC-coupled."
      },
      {
        "number": "44",
        "name": "OSCin*",
        "type": "input",
        "description": "Complementary OSCin input; feedback to PLL1 and reference input to PLL2, AC-coupled."
      },
      {
        "number": "45",
        "name": "Vcc9_CP2",
        "type": "power_in",
        "description": "Power supply for the PLL2 charge pump."
      },
      {
        "number": "46",
        "name": "CPout2",
        "type": "output",
        "description": "Charge pump 2 output."
      },
      {
        "number": "47",
        "name": "Vcc10_PLL2",
        "type": "power_in",
        "description": "Power supply for PLL2."
      },
      {
        "number": "48",
        "name": "Status_LD2",
        "type": "bidirectional",
        "description": "Programmable status pin."
      },
      {
        "number": "49",
        "name": "SDCLKout9",
        "type": "output",
        "description": "Programmable SYSREF or device clock output 9 (true side)."
      },
      {
        "number": "50",
        "name": "SDCLKout9*",
        "type": "output",
        "description": "Complementary side of programmable SYSREF or device clock output 9."
      },
      {
        "number": "51",
        "name": "DCLKout8",
        "type": "output",
        "description": "Programmable device clock output 8 (true side)."
      },
      {
        "number": "52",
        "name": "DCLKout8*",
        "type": "output",
        "description": "Complementary side of programmable device clock output 8."
      },
      {
        "number": "53",
        "name": "Vcc11_CG3",
        "type": "power_in",
        "description": "Power supply for clock outputs 8, 9, 10 and 11."
      },
      {
        "number": "54",
        "name": "DCLKout10",
        "type": "output",
        "description": "Programmable device clock output 10 (true side)."
      },
      {
        "number": "55",
        "name": "DCLKout10*",
        "type": "output",
        "description": "Complementary side of programmable device clock output 10."
      },
      {
        "number": "56",
        "name": "SDCLKout11",
        "type": "output",
        "description": "Programmable SYSREF or device clock output 11 (true side)."
      },
      {
        "number": "57",
        "name": "SDCLKout11*",
        "type": "output",
        "description": "Complementary side of programmable SYSREF or device clock output 11."
      },
      {
        "number": "58",
        "name": "CLKin_SEL0",
        "type": "bidirectional",
        "description": "Programmable status pin."
      },
      {
        "number": "59",
        "name": "CLKin_SEL1",
        "type": "bidirectional",
        "description": "Programmable status pin."
      },
      {
        "number": "60",
        "name": "SDCLKout13",
        "type": "output",
        "description": "Programmable SYSREF or device clock output 13 (true side)."
      },
      {
        "number": "61",
        "name": "SDCLKout13*",
        "type": "output",
        "description": "Complementary side of programmable SYSREF or device clock output 13."
      },
      {
        "number": "62",
        "name": "DCLKout12",
        "type": "output",
        "description": "Programmable device clock output 12 (true side)."
      },
      {
        "number": "63",
        "name": "DCLKout12*",
        "type": "output",
        "description": "Complementary side of programmable device clock output 12."
      },
      {
        "number": "64",
        "name": "Vcc12_CG0",
        "type": "power_in",
        "description": "Power supply for clock outputs 0, 1, 12 and 13."
      },
      {
        "number": "65",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin-to-name mapping is taken from the Pin Functions table on pages 3-4 (the table lists two-pin rows; The datasheet pin table prints pin 23 as 'SDCKLout5*' (transposed letters). The figure prints 'SDCLK; Pin 5 is listed as type I (CMOS input) in the table but the name also allows GPO function, so its el",
          "exposed pad 65 added from the footprint",
          "dropped thermal pad ['EP'] absent from footprint"
        ],
        "pages_sent": 13,
        "cost_usd": 0.1214,
        "at": "2026-10-08T00:57:17"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/lmk04828-ep",
        "pages": 98,
        "sha256": "533243a632b68f6f",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 65,
        "described": 65,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "lmk04828snkdrep.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9.0,
          9.0,
          0.75
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "lmk04828snkdrep-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9.0,
          9.0,
          0.75
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "b03def6fd0845b84ea00c9718f92a89e7132b6a9ada028c5dbb21815bcc7b457",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}