# LMK03328RHSR

**Texas Instruments** · Clock Generators / Frequency Synthesizers / PLL · WQFN-48-EP(7x7)

LMK03328RHSR from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STATUS0 | output | Status output 0, either open-drain (requires external pullup) or 3.3-V LVCMOS push-pull output from the synthesizer, with programmable signal selection and polarity. |
| 2 | STATUS1 | output | Status output 1, either open-drain (requires external pullup) or 3.3-V LVCMOS push-pull output from the synthesizer, with programmable signal selection and polarity. |
| 3 | CAP_DIG | passive | External bypass capacitor for the digital blocks; attach 10 µF to GND. |
| 4 | VDD_DIG | power_in | 3.3-V power supply for digital control and STATUS outputs. |
| 5 | VDD_IN | power_in | 3.3-V power supply for the input block. |
| 6 | PRIREF_P | input | Primary reference clock positive input accepting differential or single-ended signals, with internal AC-coupling capacitors and biasing; for LVCMOS input the non-driven pin must be pulled to ground. |
| 7 | PRIREF_N | input | Primary reference clock negative input accepting differential or single-ended signals, with internal AC-coupling capacitors and biasing; for LVCMOS input the non-driven pin must be pulled to ground. |
| 8 | REFSEL | input | 3-state LVCMOS manual reference input selection for PLL1 and PLL2, with weak pullup resistor. |
| 9 | HW_SW_CTRL | input | LVCMOS selection of Hard Pin Mode (ROM), Soft Pin Mode (EEPROM) or Register Default Mode, with weak pullup resistor. |
| 10 | SECREF_P | input | Secondary reference clock positive input accepting differential, single-ended or crystal input; LVCMOS swing must be attenuated to less than 2.6 V and the non-driven pin pulled to ground; crystal must be AT-cut fundamental, pullable for fine margining. |
| 11 | SECREF_N | input | Secondary reference clock negative input accepting differential, single-ended or crystal input; LVCMOS swing must be attenuated to less than 2.6 V and the non-driven pin pulled to ground. |
| 12 | GPIO0 | input | LVCMOS 2-state multifunction input (ROM page select in hard pin mode, active-low output synchronization in soft pin mode). |
| 13 | PDN | input | LVCMOS device power-down input, active low, with weak pullup resistor. |
| 14 | OUT0_P | output | Positive side of programmable output pair 0, differential or 2x 1.8-V LVCMOS. |
| 15 | OUT0_N | output | Negative side of programmable output pair 0, differential or 2x 1.8-V LVCMOS. |
| 16 | OUT1_N | output | Negative side of programmable output pair 1, differential or 2x 1.8-V LVCMOS. |
| 17 | OUT1_P | output | Positive side of programmable output pair 1, differential or 2x 1.8-V LVCMOS. |
| 18 | VDDO_01 | power_in | 1.8-V, 2.5-V or 3.3-V power supply for the OUT0/OUT1 channel. |
| 19 | VDDO_23 | power_in | 1.8-V, 2.5-V or 3.3-V power supply for the OUT2/OUT3 channel. |
| 20 | OUT2_P | output | Positive side of programmable output pair 2, differential or 2x 1.8-V LVCMOS. |
| 21 | OUT2_N | output | Negative side of programmable output pair 2, differential or 2x 1.8-V LVCMOS. |
| 22 | OUT3_N | output | Negative side of programmable output pair 3, differential or 2x 1.8-V LVCMOS. |
| 23 | OUT3_P | output | Positive side of programmable output pair 3, differential or 2x 1.8-V LVCMOS. |
| 24 | GPIO1 | input | LVCMOS multifunction input (3-state or 2-state); selects I2C target address LSBs in soft pin mode. |
| 25 | SDA | bidirectional | I2C serial data (bidirectional, open-drain); requires an external pullup resistor to VDD_DIG, and the I2C target address is initialized from on-chip EEPROM. |
| 26 | SCL | bidirectional | I2C serial clock (bidirectional, open-drain); requires an external pullup resistor to VDD_DIG. |
| 27 | VDD_PLL2 | power_in | 3.3-V power supply for PLL2. |
| 28 | CAP_PLL2 | passive | External bypass capacitor for PLL2; attach 10 µF to GND. |
| 29 | LF2 | passive | External loop filter connection for PLL2. |
| 30 | GPIO2 | input | LVCMOS multifunction input (3-state or 2-state); EEPROM page select in soft pin mode. |
| 31 | GPIO3 | input | LVCMOS multifunction input (3-state or 2-state); EEPROM page select in soft pin mode. |
| 32 | GPIO4 | input | LVCMOS multifunction input (2-state); frequency margining enable in soft pin mode. |
| 33 | GPIO5 | input | Multifunction input (2-state) or analog input for frequency margin. |
| 34 | LF1 | passive | External loop filter connection for PLL1. |
| 35 | CAP_PLL1 | passive | External bypass capacitor for PLL1; attach 10 µF to GND. |
| 36 | VDD_PLL1 | power_in | 3.3-V power supply for PLL1. |
| 37 | VDDO_4 | power_in | 1.8-V, 2.5-V or 3.3-V power supply for the OUT4 channel. |
| 38 | OUT4_N | output | Negative side of programmable output pair 4, differential or 2x 1.8-V LVCMOS. |
| 39 | OUT4_P | output | Positive side of programmable output pair 4, differential or 2x 1.8-V LVCMOS. |
| 40 | VDDO_5 | power_in | 1.8-V, 2.5-V or 3.3-V power supply for the OUT5 channel. |
| 41 | OUT5_N | output | Negative side of programmable output pair 5, differential or 2x 1.8-V LVCMOS. |
| 42 | OUT5_P | output | Positive side of programmable output pair 5, differential or 2x 1.8-V LVCMOS. |
| 43 | VDDO_6 | power_in | 1.8-V, 2.5-V or 3.3-V power supply for the OUT6 channel. |
| 44 | OUT6_N | output | Negative side of programmable output pair 6, differential or 2x 1.8-V LVCMOS. |
| 45 | OUT6_P | output | Positive side of programmable output pair 6, differential or 2x 1.8-V LVCMOS. |
| 46 | VDDO_7 | power_in | 1.8-V, 2.5-V or 3.3-V power supply for the OUT7 channel. |
| 47 | OUT7_N | output | Negative side of programmable output pair 7, differential or 2x 1.8-V LVCMOS. |
| 48 | OUT7_P | output | Positive side of programmable output pair 7, differential or 2x 1.8-V LVCMOS. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-48-EP(7x7) |
| Category | Clock and Timing |
| Pins | 49 |

## CAD (KiCad official)

- Symbol: `LMK03328RHSR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `lmk03328rhsr-etched.step` / `lmk03328rhsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmk03328rhsr.step` / `lmk03328rhsr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmk03328) (146 pp, sha256 `ba27dc3fc0d69fa7`, retrieved 2026-10-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lmk03328rhsr-datasheet.pdf)