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LMK03200ISQE

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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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LMK03200ISQE

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · WQFN-48-EP(7x7)

LMK03200ISQE from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground connection.
2 Fout output Internal VCO frequency output; tuning range 1185-1296 MHz with approximately 800 fs RMS jitter.
3 Vcc1 power_in Power supply input; rated 3.15-3.45 V.
4 CLKuWire input MICROWIRE protocol serial clock input; data clocked on rising edge.
5 DATAuWire input MICROWIRE protocol serial data input; MSB first, sampled on CLKuWire rising edge.
6 LEuWire input MICROWIRE protocol latch enable input; rising edge transfers shift register to selected register bank.
7 NC unconnected No connection.
8 Vcc2 power_in Power supply input; rated 3.15-3.45 V.
9 LDObyp1 passive LDO bypass capacitor pin; bypass with 10 µF capacitor for proper LDO operation.
10 LDObyp2 passive LDO bypass capacitor pin; bypass with 0.1 µF capacitor for proper LDO operation.
11 GOE input Global output enable input; logic high enables all clock outputs, low disables all outputs.
12 LD output Lock detect and test output; function selectable via PLL_MUX register (lock detect, frequency calibration status, or analog/divider outputs).
13 Vcc3 power_in Power supply input; rated 3.15-3.45 V.
14 CLKout0 output LVDS differential clock output 0, positive; 250-450 mV differential voltage to 50 Ω load.
15 CLKout0* output LVDS differential clock output 0, negative; complementary to CLKout0.
16 Vcc4 power_in Power supply input; rated 3.15-3.45 V.
17 CLKout1 output LVDS differential clock output 1, positive; 250-450 mV differential voltage to 50 Ω load.
18 CLKout1* output LVDS differential clock output 1, negative; complementary to CLKout1.
19 Vcc5 power_in Power supply input; rated 3.15-3.45 V.
20 CLKout2 output LVDS differential clock output 2, positive; 250-450 mV differential voltage to 50 Ω load.
21 CLKout2* output LVDS differential clock output 2, negative; complementary to CLKout2.
22 Vcc6 power_in Power supply input; rated 3.15-3.45 V.
23 CLKout3 output LVPECL differential clock output 3, positive; 660-965 mV differential voltage to 50 Ω load.
24 CLKout3* output LVPECL differential clock output 3, negative; complementary to CLKout3.
25 GND power_in Ground connection.
26 Vcc7 power_in Power supply input; rated 3.15-3.45 V.
27 SYNC* input Global clock output synchronization input; active low, internal pull-up resistor, minimum low pulse duration ≥ one VCO divider cycle.
28 OSCin input Oscillator reference clock input, positive; AC coupled, 1-200 MHz, 0.2-1.6 V differential input voltage.
29 OSCin* input Oscillator reference clock input, negative; AC coupled, 1-200 MHz, 0.2-1.6 V differential input voltage.
30 Vcc8 power_in Power supply input; rated 3.15-3.45 V.
31 Vcc9 power_in Power supply input; rated 3.15-3.45 V.
32 CPout output Charge pump output for external loop filter connection; bias point stabilizes at approximately Vcc/2.
33 Vcc10 power_in Power supply input; rated 3.15-3.45 V.
34 FBCLKin input External feedback clock input for 0-delay mode, positive; AC coupled, 1-800 MHz, 0.2-1.6 V differential input voltage.
35 FBCLKin* input External feedback clock input for 0-delay mode, negative; AC coupled, 1-800 MHz, 0.2-1.6 V differential input voltage.
36 Bias passive Bias bypass capacitor pin; bypass with 1 µF low-leakage capacitor to Vcc for low-noise operation.
37 Vcc11 power_in Power supply input; rated 3.15-3.45 V.
38 CLKout4 output LVPECL differential clock output 4, positive; 660-965 mV differential voltage to 50 Ω load.
39 CLKout4* output LVPECL differential clock output 4, negative; complementary to CLKout4.
40 Vcc12 power_in Power supply input; rated 3.15-3.45 V.
41 CLKout5 output LVPECL differential clock output 5, positive; can be routed for internal 0-delay feedback path.
42 CLKout5* output LVPECL differential clock output 5, negative; complementary to CLKout5.
43 Vcc13 power_in Power supply input; rated 3.15-3.45 V.
44 CLKout6 output LVPECL differential clock output 6, positive; can be routed for internal 0-delay feedback path.
45 CLKout6* output LVPECL differential clock output 6, negative; complementary to CLKout6.
46 Vcc14 power_in Power supply input; rated 3.15-3.45 V.
47 CLKout7 output LVPECL differential clock output 7, positive; 660-965 mV differential voltage to 50 Ω load.
48 CLKout7* output LVPECL differential clock output 7, negative; complementary to CLKout7.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Clock/Timing
Pins 49

CAD (KiCad official)

  • Symbol: LMK03200ISQE
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: lmk03200isqe-etched.step / lmk03200isqe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk03200isqe.step / lmk03200isqe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 6f10a8696c555da4, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF