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LMK00804BQWRGTTQ1
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Texas Instruments Clock Buffers, Drivers, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+54@@ -0,0 +1,54 @@+# LMK00804BQWRGTTQ1++**Texas Instruments** · Clock Buffers, Drivers · VQFN-16-EP(3x3)++LMK00804BQWRGTTQ1 from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Power supply ground. |+| 2 | NC | unconnected | No-connect pin, typically left floating and not to be connected to GND. |+| 3 | VDD | power_in | Power supply terminal, typically 3.3 V (recommended 3.135 V to 3.465 V), with a typical 0.1 µF decoupling capacitor to GND. |+| 4 | CLK_EN | input | Synchronous clock enable input that must be held low until a valid reference clock is provided; low forces outputs to logic low and high enables the LVCMOS/LVTTL outputs, with an internal pullup (typically 1 kΩ to VDD external) and left floating when unused. |+| 5 | CLK_P | input | Noninverting differential clock input with internal 51 kΩ (typ) pulldown to GND, which can also accept a single-ended clock; leave floating when unused. |+| 6 | CLK_N | input | Inverting differential clock input with internal 51 kΩ (typ) pullup to VDD and 51 kΩ (typ) pulldown to GND, internally biased to VDD/2 when floating. |+| 7 | CLK_SEL | input | Clock select input, typically pulled up to VDD with an external 1 kΩ; low selects LVCMOS_CLK (pin 8) and high selects CLK_P/CLK_N (pins 5, 6). |+| 8 | LVCMOS_CLK | input | Single-ended clock input with internal 51 kΩ (typ) pulldown to GND that accepts LVCMOS/LVTTL levels; leave floating when unused. |+| 9 | GND | power_in | Power supply ground. |+| 10 | Q3 | output | Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused. |+| 11 | VDDO | power_in | Output supply terminal, typically 3.3 V, 2.5 V, 1.8 V or 1.5 V, with a typical 0.1 µF decoupling capacitor to GND. |+| 12 | Q2 | output | Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused. |+| 13 | GND | power_in | Power supply ground. |+| 14 | Q1 | output | Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused. |+| 15 | VDDO | power_in | Output supply terminal, typically 3.3 V, 2.5 V, 1.8 V or 1.5 V, with a typical 0.1 µF decoupling capacitor to GND. |+| 16 | Q0 | output | Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused. |+| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-16-EP(3x3) |+| Category | RTC/Clock Chip |+| Pins | 17 |++## CAD (KiCad official)++- Symbol: `LMK00804BQWRGTTQ1`+- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`+- 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)+- 3D model files: `lmk00804bqwrgttq1-etched.step` / `lmk00804bqwrgttq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmk00804bqwrgttq1.step` / `lmk00804bqwrgttq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmk00804b-q1) (29 pp, sha256 `b58ecb79387c6fb9`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lmk00804bqwrgttq1-datasheet.pdf)
page.jsonadded+255@@ -0,0 +1,255 @@+{+ "slug": "lmk00804bqwrgttq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Buffers, Drivers, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "rtc-clock chip",+ "lmk00804bqwrgttq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lmk00804bqwrgttq1.kicad_sym",+ "lmk00804bqwrgttq1.kicad_mod",+ "lmk00804bqwrgttq1.glb",+ "lmk00804bqwrgttq1.step",+ "lmk00804bqwrgttq1.lbr",+ "docs/hero.png",+ "docs/lmk00804bqwrgttq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lmk00804bqwrgttq1-hero.glb",+ "lmk00804bqwrgttq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "LMK00804BQWRGTTQ1",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-16-EP(3x3)",+ "pin_count": 17,+ "category": "RTC/Clock Chip",+ "subcategory": "Clock Buffers, Drivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lmk00804b-q1",+ "parts": {+ "symbol": "lmk00804bqwrgttq1.kicad_sym",+ "footprint": "lmk00804bqwrgttq1.kicad_mod",+ "model_3d": "lmk00804bqwrgttq1-hero.glb",+ "model_3d_plain": "lmk00804bqwrgttq1.glb",+ "model_3d_step": "lmk00804bqwrgttq1-etched.step",+ "model_3d_step_plain": "lmk00804bqwrgttq1.step",+ "lbr": "lmk00804bqwrgttq1.lbr"+ },+ "distributor_links": {+ "lcsc": "C1520152",+ "digikey": "296-LMK00804BQWRGTTQ1TR-ND",+ "mouser": "595-MK00804BQWRGTTQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T00:40:16Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-LMK00804BQWRGTTQ1TR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-MK00804BQWRGTTQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Power supply ground."+ },+ {+ "number": "2",+ "name": "NC",+ "type": "unconnected",+ "description": "No-connect pin, typically left floating and not to be connected to GND."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "Power supply terminal, typically 3.3 V (recommended 3.135 V to 3.465 V), with a typical 0.1 µF decoupling capacitor to GND."+ },+ {+ "number": "4",+ "name": "CLK_EN",+ "type": "input",+ "description": "Synchronous clock enable input that must be held low until a valid reference clock is provided; low forces outputs to logic low and high enables the LVCMOS/LVTTL outputs, with an internal pullup (typically 1 kΩ to VDD external) and left floating when unused."+ },+ {+ "number": "5",+ "name": "CLK_P",+ "type": "input",+ "description": "Noninverting differential clock input with internal 51 kΩ (typ) pulldown to GND, which can also accept a single-ended clock; leave floating when unused."+ },+ {+ "number": "6",+ "name": "CLK_N",+ "type": "input",+ "description": "Inverting differential clock input with internal 51 kΩ (typ) pullup to VDD and 51 kΩ (typ) pulldown to GND, internally biased to VDD/2 when floating."+ },+ {+ "number": "7",+ "name": "CLK_SEL",+ "type": "input",+ "description": "Clock select input, typically pulled up to VDD with an external 1 kΩ; low selects LVCMOS_CLK (pin 8) and high selects CLK_P/CLK_N (pins 5, 6)."+ },+ {+ "number": "8",+ "name": "LVCMOS_CLK",+ "type": "input",+ "description": "Single-ended clock input with internal 51 kΩ (typ) pulldown to GND that accepts LVCMOS/LVTTL levels; leave floating when unused."+ },+ {+ "number": "9",+ "name": "GND",+ "type": "power_in",+ "description": "Power supply ground."+ },+ {+ "number": "10",+ "name": "Q3",+ "type": "output",+ "description": "Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused."+ },+ {+ "number": "11",+ "name": "VDDO",+ "type": "power_in",+ "description": "Output supply terminal, typically 3.3 V, 2.5 V, 1.8 V or 1.5 V, with a typical 0.1 µF decoupling capacitor to GND."+ },+ {+ "number": "12",+ "name": "Q2",+ "type": "output",+ "description": "Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused."+ },+ {+ "number": "13",+ "name": "GND",+ "type": "power_in",+ "description": "Power supply ground."+ },+ {+ "number": "14",+ "name": "Q1",+ "type": "output",+ "description": "Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused."+ },+ {+ "number": "15",+ "name": "VDDO",+ "type": "power_in",+ "description": "Output supply terminal, typically 3.3 V, 2.5 V, 1.8 V or 1.5 V, with a typical 0.1 µF decoupling capacitor to GND."+ },+ {+ "number": "16",+ "name": "Q0",+ "type": "output",+ "description": "Single-ended clock output with LVCMOS/LVTTL levels at 7 Ω output impedance, typically driven into a 43 Ω series termination; leave unconnected when unused."+ },+ {+ "number": "17",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The thermal pad on the RGT VQFN package is shown in the top-view drawing but is not given a pin numb; Pin types were mapped to KiCad ERC classes: VDD and VDDO are supply inputs and were set to power_in,",+ "exposed pad 17 added from the footprint"+ ],+ "pages_sent": 9,+ "cost_usd": 0.0634,+ "at": "2026-10-08T00:40:00"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lmk00804b-q1",+ "pages": 29,+ "sha256": "b58ecb79387c6fb9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lmk00804bqwrgttq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3,+ 3,+ 0.785+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lmk00804bqwrgttq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3,+ 3,+ 0.785+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "87031ef8dd2692187dd519e7a534eeea2851efffb986cca27c5a6994f44c1e6e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}