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LMK00334RTVTQ1

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Texas Instruments Clock Buffers, Drivers, Distributors, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LMK00334RTVTQ1

Texas Instruments · Clock Buffers, Drivers, Distributors · WQFN-32-EP(5x5)

LMK00334RTVTQ1 from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin.
2 VCCOA power_in Power supply for Bank A output buffers, operating from 3.3 V or 2.5 V (each within ±5%); the VCCOA pins are internally tied together and each should be bypassed with a 0.1-µF low-ESR capacitor.
3 CLKoutA0 output Differential clock output A0 (HCSL or Hi-Z selectable).
4 CLKoutA0* output Complementary differential clock output A0 (HCSL or Hi-Z selectable).
5 VCCOA power_in Power supply for Bank A output buffers, operating from 3.3 V or 2.5 V (each within ±5%); the VCCOA pins are internally tied together and each should be bypassed with a 0.1-µF low-ESR capacitor.
6 CLKoutA1 output Differential clock output A1 (HCSL or Hi-Z selectable).
7 CLKoutA1* output Complementary differential clock output A1 (HCSL or Hi-Z selectable).
8 GND power_in Ground pin.
9 CLKout_EN input Low-active enable for the Bank A and Bank B output buffers; CMOS control input with an internal pulldown resistor.
10 VCC power_in Core and input buffer supply operating from 3.3 V (3.15 V to 3.45 V recommended); bypass with a 0.1-µF low-ESR capacitor placed very close to each VCC pin.
11 OSCin input Crystal input, which can also be driven by an XO, TCXO, or other external single-ended clock; the device supports 10 MHz to 40 MHz crystals or single-ended clocks.
12 OSCout output Crystal output; leave floating if OSCin is driven by a single-ended clock.
13 CLKin_SEL0 input Clock input selection pin (CMOS control input with internal pulldown resistor).
14 CLKin0 input Universal clock input 0, accepting differential (LVPECL, LVDS, CML, SSTL, HSTL, HCSL) or single-ended clocks at operating frequencies up to 400 MHz.
15 CLKin0* input Complementary universal clock input 0, accepting differential (LVPECL, LVDS, CML, SSTL, HSTL, HCSL) or single-ended clocks at operating frequencies up to 400 MHz.
16 CLKin_SEL1 input Clock input selection pin (CMOS control input with internal pulldown resistor).
17 GND power_in Ground pin.
18 CLKoutB1* output Complementary differential clock output B1 (HCSL or Hi-Z selectable).
19 CLKoutB1 output Differential clock output B1 (HCSL or Hi-Z selectable).
20 VCCOB power_in Power supply for Bank B output buffers, operating from 3.3 V or 2.5 V (each within ±5%); the VCCOB pins are internally tied together and each should be bypassed with a 0.1-µF low-ESR capacitor.
21 CLKoutB0* output Complementary differential clock output B0 (HCSL or Hi-Z selectable).
22 CLKoutB0 output Differential clock output B0 (HCSL or Hi-Z selectable).
23 VCCOB power_in Power supply for Bank B output buffers, operating from 3.3 V or 2.5 V (each within ±5%); the VCCOB pins are internally tied together and each should be bypassed with a 0.1-µF low-ESR capacitor.
24 GND power_in Ground pin.
25 NC unconnected Not connected internally; may be floated, grounded, or tied to any potential within the Supply Voltage range in the Absolute Maximum Ratings.
26 CLKin1* input Complementary universal clock input 1, accepting differential (LVPECL, LVDS, CML, SSTL, HSTL, HCSL) or single-ended clocks at operating frequencies up to 400 MHz.
27 CLKin1 input Universal clock input 1, accepting differential (LVPECL, LVDS, CML, SSTL, HSTL, HCSL) or single-ended clocks at operating frequencies up to 400 MHz.
28 VCC power_in Core and input buffer supply operating from 3.3 V (3.15 V to 3.45 V recommended); bypass with a 0.1-µF low-ESR capacitor placed very close to each VCC pin.
29 REFout output LVCMOS reference output, enabled by pulling REFout_EN high.
30 VCCOC power_in Power supply for the REFout buffer, operating from 3.3 V or 2.5 V (each within ±5%); bypass with a 0.1-µF low-ESR capacitor.
31 REFout_EN input REFout enable input, internally synchronized to the selected clock input (CMOS control input with internal pulldown resistor).
32 VCC power_in Core and input buffer supply operating from 3.3 V (3.15 V to 3.45 V recommended); bypass with a 0.1-µF low-ESR capacitor placed very close to each VCC pin.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Clock/Timing
Pins 33

CAD (KiCad official)

  • Symbol: LMK00334RTVTQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lmk00334rtvtq1-etched.step / lmk00334rtvtq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk00334rtvtq1.step / lmk00334rtvtq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 d226e24823665475, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF