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LMK00334RTVR

Public Made by Adom

by adom

Texas Instruments Clock Buffers, Drivers, Distributors, WQFN-32-EP(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs lmk00334rtvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers lmk00334rtvr: viewers · Ray 28d ago
lmk00334rtvr-etched.fit.json lmk00334rtvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
lmk00334rtvr-etched.glb lmk00334rtvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
lmk00334rtvr-etched.step lmk00334rtvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
lmk00334rtvr.glb Publish 0.1.0 · Ray 28d ago
lmk00334rtvr.kicad_mod Publish 0.1.0 · Ray 28d ago
lmk00334rtvr.kicad_sym Publish 0.1.0 · Ray 28d ago
lmk00334rtvr.lbr Publish 0.1.0 · Ray 28d ago
lmk00334rtvr.step Publish 0.1.0 · Ray 28d ago
package.json Publish 0.1.0 · Ray 28d ago
page.json lmk00334rtvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1d ago
README.md lmk00334rtvr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago

LMK00334RTVR

Texas Instruments · Clock Buffers, Drivers, Distributors · WQFN-32-EP(5x5)

LMK00334RTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground return.
2 VCCOA power_in Output supply for Bank A output buffers. 3.3 V or 2.5 V. Pin 2 and pin 5 are internally connected; bypass with 0.1 µF low-ESR capacitor near each pin.
3 CLKoutA0 output Differential clock output A0 (true). HCSL or Hi-Z.
4 CLKoutA0* output Differential clock output A0 (complement). HCSL or Hi-Z.
5 VCCOA power_in Output supply for Bank A output buffers. 3.3 V or 2.5 V. Internally tied to pin 2; bypass with 0.1 µF near pin.
6 CLKoutA1 output Differential clock output A1 (true). HCSL or Hi-Z.
7 CLKoutA1* output Differential clock output A1 (complement). HCSL or Hi-Z.
8 GND power_in Ground return.
9 CLKout_EN input Bank A and Bank B output enable, active-high. CMOS control input with internal pulldown.
10 VCC power_in Core and input buffer supply. 3.3 V. Bypass each VCC pin with a 0.1 µF low-ESR capacitor.
11 OSCin input Crystal input; may also be driven by an XO/TCXO or other external single-ended clock.
12 OSCout output Crystal output. If OSCin is driven by a single-ended clock, OSCout should be left floating.
13 CLKin_SEL0 input Clock input MUX select 0. CMOS control input with internal pulldown.
14 CLKin0 input Universal clock input 0, true (differential or single-ended).
15 CLKin0* input Universal clock input 0, complement (differential or single-ended).
16 CLKin_SEL1 input Clock input MUX select 1. CMOS control input with internal pulldown.
17 GND power_in Ground return.
18 CLKoutB1* output Differential clock output B1 (complement). HCSL or Hi-Z.
19 CLKoutB1 output Differential clock output B1 (true). HCSL or Hi-Z.
20 VCCOB power_in Output supply for Bank B output buffers. 3.3 V or 2.5 V. Pin 20 and pin 23 are internally tied; bypass with 0.1 µF near each pin.
21 CLKoutB0* output Differential clock output B0 (complement). HCSL or Hi-Z.
22 CLKoutB0 output Differential clock output B0 (true). HCSL or Hi-Z.
23 VCCOB power_in Output supply for Bank B output buffers. 3.3 V or 2.5 V. Internally tied to pin 20; bypass with 0.1 µF near pin.
24 GND power_in Ground return.
25 NC unconnected No internal connection. May be left floating, tied to GND, or tied to any potential within the Absolute Maximum supply range.
26 CLKin1* input Universal clock input 1, complement (differential or single-ended).
27 CLKin1 input Universal clock input 1, true (differential or single-ended).
28 VCC power_in Core and input buffer supply. 3.3 V. Bypass with 0.1 µF low-ESR capacitor near pin.
29 REFout output LVCMOS reference output. Enabled by driving REFout_EN high.
30 VCCOC power_in Supply for the REFout buffer. 3.3 V or 2.5 V. Bypass with 0.1 µF low-ESR capacitor near pin.
31 REFout_EN input REFout enable, active-high. Also synchronizes REFout with the selected clock input internally. CMOS input with internal pulldown.
32 VCC power_in Core and input buffer supply. 3.3 V. Bypass with 0.1 µF low-ESR capacitor near pin.
DAP DAP power_in Die attach pad. Must be soldered to the PCB ground plane for thermal dissipation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Clock/Timing
Pins 33

Ordering variants

Same part, different packaging or reel option.

  • LMK00334RTVR
  • LMK00334RTVRRTVT

CAD (KiCad official)

  • Symbol: LMK00334RTVR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lmk00334rtvr-etched.step / lmk00334rtvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk00334rtvr.step / lmk00334rtvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 0fea59e58d9782db, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF