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LMK00101SQE

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by adom

Texas Instruments Clock Buffers, Drivers, Distributors, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LMK00101SQE

Texas Instruments · Clock Buffers, Drivers, Distributors · WQFN-32-EP(5x5)

LMK00101SQE from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKout0 output LVCMOS clock output, Bank A.
2 Vddo power_in Output supply for Bank A (CLKout0 to CLKout4); Vddo must be between 1.425 V and Vdd (Vddo ≤ Vdd).
3 CLKout1 output LVCMOS clock output, Bank A.
4 GND power_in Ground pin.
5 CLKout2 output LVCMOS clock output, Bank A.
6 Vddo power_in Output supply for Bank A (CLKout0 to CLKout4); Vddo must be between 1.425 V and Vdd (Vddo ≤ Vdd).
7 CLKout3 output LVCMOS clock output, Bank A.
8 CLKout4 output LVCMOS clock output, Bank A.
9 GND power_in Ground pin.
10 Vdd power_in Core supply for the operating core and input buffer; 2.375 V to 3.45 V (3.3 V typical).
11 OSCin input Input for the crystal oscillator.
12 OSCout output Output for the crystal oscillator.
13 CLKin0 input Input pin for clock input 0.
14 CLKin0* input Complementary input pin for clock input 0.
15 GND power_in Ground pin.
16 GND power_in Ground pin.
17 CLKout5 output LVCMOS clock output, Bank B.
18 CLKout6 output LVCMOS clock output, Bank B.
19 Vddo power_in Output supply for Bank B (CLKout5 to CLKout9); Vddo must be between 1.425 V and Vdd (Vddo ≤ Vdd).
20 CLKout7 output LVCMOS clock output, Bank B.
21 GND power_in Ground pin.
22 CLKout8 output LVCMOS clock output, Bank B.
23 Vddo power_in Output supply for Bank B (CLKout5 to CLKout9); Vddo must be between 1.425 V and Vdd (Vddo ≤ Vdd).
24 CLKout9 output LVCMOS clock output, Bank B.
25 GND power_in Ground pin.
26 GND power_in Ground pin.
27 CLKin1* input Complementary input pin for clock input 1.
28 CLKin1 input Input pin for clock input 1.
29 SEL1 input MSB for input clock selection; internal pull-down resistor.
30 SEL0 input LSB for input clock selection; internal pull-down resistor.
31 OE input Output enable; CMOS control input with internal pull-down resistor.
32 GND power_in Ground pin.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Clock/Timing
Pins 33

CAD (KiCad official)

  • Symbol: LMK00101SQE
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lmk00101sqe-etched.step / lmk00101sqe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk00101sqe.step / lmk00101sqe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 c4025a08528c68a4, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF