component

LMK00101SQ

Public Made by Adom

by adom

Texas Instruments Clock Buffers, Drivers, Distributors, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock-timinglmk00101sqfactory-2.0.0extractor-text

Verified LMK00101SQ

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LMK00101SQ · WQFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 22-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ehkbqt9q/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lmk00101sq.kicad_sym✓ lmk00101sq.kicad_mod✓ lmk00101sq.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2h ago
viewers lmk00101sq: viewers · Ray 2h ago
lmk00101sq-etched.glb Publish 0.1.0 · Ray 2h ago
lmk00101sq-etched.step lmk00101sq: factory component page (tier=mfr) · Ray 2h ago
lmk00101sq-hero.glb lmk00101sq: hero GLB from the etched model (keeps the MPN mark) · Ray 2h ago
lmk00101sq-hero.overlay.json Publish 0.1.0 · Ray 2h ago
lmk00101sq.glb Publish 0.1.0 · Ray 2h ago
lmk00101sq.kicad_mod Publish 0.1.0 · Ray 2h ago
lmk00101sq.kicad_sym Publish 0.1.0 · Ray 2h ago
lmk00101sq.lbr Publish 0.1.0 · Ray 2h ago
lmk00101sq.step Publish 0.1.0 · Ray 2h ago
package.json Publish 0.1.0 · Ray 2h ago
page.json Set visibility: public · Ray 2h ago
README.md Publish 0.1.0 · Ray 2h ago
verification.json Verified: Published by the parts factory: tier mfr, 33 pins · Ray 2h ago

LMK00101SQ

Texas Instruments · Clock Buffers, Drivers, Distributors · WQFN-32-EP(5x5)

LMK00101SQ from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKout0 output LVCMOS clock output in Bank A, powered from the Bank A Vddo supply (1.425 V to Vdd).
2 Vddo power_in Output supply for Bank A (CLKout0 to CLKout4); Vddo must be less than or equal to Vdd.
3 CLKout1 output LVCMOS clock output in Bank A, powered from the Bank A Vddo supply.
4 GND power_in Ground connection.
5 CLKout2 output LVCMOS clock output in Bank A, powered from the Bank A Vddo supply.
6 Vddo power_in Output supply for Bank A (CLKout0 to CLKout4); Vddo must be less than or equal to Vdd.
7 CLKout3 output LVCMOS clock output in Bank A, powered from the Bank A Vddo supply.
8 CLKout4 output LVCMOS clock output in Bank A, powered from the Bank A Vddo supply.
9 GND power_in Ground connection.
10 Vdd power_in Core supply for operating the core and input buffer, 2.375 V to 3.45 V.
11 OSCin input Input for crystal oscillator, 10 to 40 MHz crystal input frequency.
12 OSCout output Output for crystal oscillator.
13 CLKin0 input Universal clock input pin, accepting LVPECL, LVDS, HCSL, SSTL or LVCMOS signals.
14 CLKin0* input Complementary clock input pin paired with CLKin0.
15 GND power_in Ground connection.
16 GND power_in Ground connection.
17 CLKout5 output LVCMOS clock output in Bank B, powered from the Bank B Vddo supply.
18 CLKout6 output LVCMOS clock output in Bank B, powered from the Bank B Vddo supply.
19 Vddo power_in Output supply for Bank B (CLKout5 to CLKout9); Vddo must be less than or equal to Vdd.
20 CLKout7 output LVCMOS clock output in Bank B, powered from the Bank B Vddo supply.
21 GND power_in Ground connection.
22 CLKout8 output LVCMOS clock output in Bank B, powered from the Bank B Vddo supply.
23 Vddo power_in Output supply for Bank B (CLKout5 to CLKout9); Vddo must be less than or equal to Vdd.
24 CLKout9 output LVCMOS clock output in Bank B, powered from the Bank B Vddo supply.
25 GND power_in Ground connection.
26 GND power_in Ground connection.
27 CLKin1* input Complementary clock input pin paired with CLKin1.
28 CLKin1 input Universal clock input pin, accepting LVPECL, LVDS, HCSL, SSTL or LVCMOS signals.
29 SEL1 input MSB for input clock selection; internal pull-down resistor present.
30 SEL0 input LSB for input clock selection; internal pull-down resistor present.
31 OE input Output enable, synchronous to the outputs for glitch-free operation; internal pull-down resistor present.
32 GND power_in Ground connection.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Clock/Timing
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient Temperature TA -40 25 85 °C 3
Core Supply Voltage Vdd 2.375 3.3 3.45 V 3
Output Supply Voltage Vddo 1.425 3.3 V Vddo should be less than or equal to Vdd (Vddo ≤ Vdd) 3
Core Supply Voltage Vdd -0.3 3.6 V 3
Output Supply Voltage Vddo -0.3 3.6 V 3
Input Voltage VIN -0.3 V upper limit Vdd + 0.3 V as printed 3
Storage Temperature Range TSTG -65 150 °C 3
Lead Temperature TL 260 °C solder 4 s 3
Junction Temperature TJ 125 °C 3
Thermal resistance junction to ambient θJA 50 °C/W on 4-layer Jedec board 3
Thermal resistance junction to case (DAP) θJC 20 °C/W junction to case (DAP) 3
Core Supply Voltage Vdd 2.375 3.45 V 4
Output Supply Voltage Vddo 1.425 V 4
Output Skew 6 25 ps Measured between outputs, referenced to CLKout0 4
Propagation Delay CLKin to CLKout tPD 0.85 1.4 2.2 ns CL = 5 pF, RL = 50 Ω; Vdd = 3.3 V; Vddo = 3.3 V 4
Propagation Delay CLKin to CLKout tPD 1.1 1.8 2.8 ns CL = 5 pF, RL = 50 Ω; Vdd = 2.5 V; Vddo = 1.5 V 4
Part-to-part Skew tPD, PP 0.35 ns CL = 5 pF, RL = 50 Ω; Vdd = 3.3 V; Vddo = 3.3 V 4
Part-to-part Skew tPD, PP 0.6 ns CL = 5 pF, RL = 50 Ω; Vdd = 2.5 V; Vddo = 1.5 V 4
Output Frequency fCLKout 200 MHz 4
Rise/Fall Time tRise 250 ps Vdd = 3.3 V, Vddo = 1.8 V, CL = 10 pF 4
Rise/Fall Time tRise 275 ps Vdd = 2.5 V, Vddo = 2.5 V, CL = 10 pF 4
Rise/Fall Time tRise 315 ps Vdd = 3.3 V, Vddo = 3.3 V, CL = 10 pF 4
Output Low Voltage VCLKoutLow 0.1 V 4
Output Resistance RCLKout 50 ohm 4
Digital Input Low Voltage VLow 0.4 V Vdd = 2.5 V 5
Digital Input High Voltage VHigh 1.3 V Vdd = 2.5 V 5
Digital Input High Voltage VHigh 1.6 V Vdd = 3.3 V 5
High Level Input Current IIH 50 uA 5
Low Level Input Current IIL -5 5 uA 5
High Level Input Current IIH 20 uA VCLKin = Vdd 5
Low Level Input Current IIL -20 uA VCLKin = 0 V 5
Differential Input Common Mode Voltage VCM 0.5 1.2 V VID = 150 mV 5
Differential Input Common Mode Voltage VCM 0.5 1.1 V VID = 350 mV 5
Differential Input Common Mode Voltage VCM 0.5 0.9 V VID = 800 mV 5
Single-Ended Input Voltage Swing VI_SE 0.3 2 Vpp CLKinX driven single-ended (AC or DC coupled), CLKinX* AC coupled to GND or externally biased within VCM range 5
Differential Input Voltage Swing VID 0.15 1.5 V CLKin driven differentially 5
Input Frequency fOSCin 200 MHz Single-Ended Input 5
Crystal Frequency Input Range fXTAL 10 40 MHz ESR < 200 Ω ( fXtal ≤ 30 MHz ) 5
Input High Voltage VIH 2.5 V Single-Ended Input, OSCout floating 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper For best soldering practices, the minimum trace length should extend to include the pin solder mask. This way during reflow, the solder has the same copper area as connected 9

CAD (KiCad official)

  • Symbol: LMK00101SQ
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lmk00101sq-etched.step / lmk00101sq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk00101sq.step / lmk00101sq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 4286d2ddc5501394, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF