LMH6521SQ

Texas Instruments · Special Purpose Amplifiers · WQFN-32-EP(5x5)

LMH6521SQ from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A3/SDI/DNA	input	Parallel mode A3 is attenuation bit three (4-dB step), serial mode SDI is serial data in (SPI), and pulse mode DNA is the down pulse pin where a logic 0 pulse decreases gain one step; pulsing with pin 2 resets gain to maximum.
2	A4/CLK/UPA	input	Parallel mode A4 is attenuation bit four (8-dB step), serial mode CLK is the serial clock (SPI), and pulse mode UPA is the up pulse pin where a logic 0 pulse increases gain one step; pulsing with pin 1 resets gain to maximum.
3	A5	input	Attenuation bit five (16-dB step) in parallel mode; unused in serial and pulse modes and connected to DC ground.
4	MOD0	input	Digital mode control pin that floats to logic high if unconnected; set with MOD1 to select parallel, serial or pulse mode (MOD0=0 in serial mode).
5	MOD1	input	Digital mode control pin that floats to logic high if unconnected; set with MOD0 to select parallel, serial or pulse mode (MOD1=0 in pulse mode).
6	B5	input	Attenuation bit five (16-dB step) for channel B in parallel mode; unused in serial and pulse modes and connected to DC ground.
7	B4/UPB	input	Parallel mode B4 is attenuation bit four (8-dB step) and pulse mode UPB is the up pulse pin (logic 0 pulse increases gain one step); pulsing with pin 8 resets gain to maximum; connect to DC ground in serial mode.
8	B3/DNB	input	Parallel mode B3 is attenuation bit three (4-dB step) and pulse mode DNB is the down pulse pin (logic 0 pulse decreases gain one step); pulsing with pin 7 resets gain to maximum; connect to DC ground in serial mode.
9	B2/S1B	input	Parallel mode B2 is attenuation bit two (2-dB step) and pulse mode S1B is step size bit 1 ((0,0)=0.5 dB, (0,1)=1 dB, (1,0)=2 dB, (1,1)=6 dB); connect to DC ground in serial mode.
10	B1/S0B	input	Parallel mode B1 is attenuation bit one (1-dB step) and pulse mode S0B is step size bit 0 ((0,0)=0.5 dB, (0,1)=1 dB, (1,0)=2 dB, (1,1)=6 dB); connect to DC ground in serial mode.
11	INB+	input	Channel B noninverting amplifier input, internally biased to mid supply; input voltage must not exceed V+ or go below GND by more than 0.5 V.
12	INB-	input	Channel B inverting amplifier input, internally biased to mid supply; input voltage must not exceed V+ or go below GND by more than 0.5 V.
13	GND	power_in	Ground pin to connect to a low impedance ground plane; all pin voltages are specified with respect to these pins and the exposed pad is internally bonded to them.
14	+5V	power_in	Power supply pin with a valid range of 4.75 V to 5.25 V.
15	GND	power_in	Ground pin to connect to a low impedance ground plane; all pin voltages are specified with respect to these pins and the exposed pad is internally bonded to them.
16	B0	input	Attenuation bit zero (0.5-dB step) for channel B in parallel mode, where 000000 is maximum gain; connect to DC ground in serial and pulse modes.
17	OUTB+	output	Channel B noninverting amplifier output, externally biased to 0 V.
18	OUTB-	output	Channel B inverting amplifier output, externally biased to 0 V.
19	ENB	input	Channel B enable pin, logic 1 = enabled state; floats high if left unconnected.
20	LATB	input	Channel B latch pin in parallel mode (logic 0 = active, logic 1 = latched, gain unchanged once high); connect to ground if latch is not desired or in serial and pulse modes.
21	LATA	input	Channel A latch pin in parallel mode (logic 0 = active, logic 1 = latched, gain unchanged once high); connect to ground if latch is not desired or in serial and pulse modes.
22	ENA	input	Channel A enable pin, logic 1 = enabled state; floats high if left unconnected.
23	OUTA-	output	Channel A inverting amplifier output, externally biased to 0 V.
24	OUTA+	output	Channel A noninverting amplifier output, externally biased to 0 V.
25	A0	input	Attenuation bit zero (0.5-dB step) for channel A in parallel mode, where 000000 is maximum gain; connect to DC ground in pulse mode and leave NC in serial mode per Table 1.
26	GND	power_in	Ground pin to connect to a low impedance ground plane; all pin voltages are specified with respect to these pins and the exposed pad is internally bonded to them.
27	+5V	power_in	Power supply pin with a valid range of 4.75 V to 5.25 V.
28	GND	power_in	Ground pin to connect to a low impedance ground plane; all pin voltages are specified with respect to these pins and the exposed pad is internally bonded to them.
29	INA-	input	Channel A inverting amplifier input, internally biased to mid supply; input voltage must not exceed V+ or go below GND by more than 0.5 V.
30	INA+	input	Channel A noninverting amplifier input, internally biased to mid supply; input voltage must not exceed V+ or go below GND by more than 0.5 V.
31	A1/SDO/S0A	input	Parallel mode A1 is attenuation bit one (1-dB step), serial mode SDO is serial data out (SPI), and pulse mode S0A is step size bit 0 ((0,0)=0.5 dB, (0,1)=1 dB, (1,0)=2 dB, (1,1)=6 dB).
32	A2/CS/S1A	input	Parallel mode A2 is attenuation bit two (2-dB step), serial mode CS is the active-low chip select (SPI), and pulse mode S1A is step size bit 1 ((0,0)=0.5 dB, (0,1)=1 dB, (1,0)=2 dB, (1,1)=6 dB).
33	GND	power_in	Exposed thermal pad, connect to a low impedance ground plane; it is internally bonded to the ground pins.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-32-EP(5x5)
Category	Operational Amplifier/Comparator
Pins	33

CAD (KiCad official)

Symbol: LMH6521SQ
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: lmh6521sq-etched.step / lmh6521sq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmh6521sq.step / lmh6521sq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (38 pp, sha256 73c886f243e5aa0c, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# LMH6521SQ

**Texas Instruments** · Special Purpose Amplifiers · WQFN-32-EP(5x5)

LMH6521SQ from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A3/SDI/DNA | input | Parallel mode A3 is attenuation bit three (4-dB step), serial mode SDI is serial data in (SPI), and pulse mode DNA is the down pulse pin where a logic 0 pulse decreases gain one step; pulsing with pin 2 resets gain to maximum. |
| 2 | A4/CLK/UPA | input | Parallel mode A4 is attenuation bit four (8-dB step), serial mode CLK is the serial clock (SPI), and pulse mode UPA is the up pulse pin where a logic 0 pulse increases gain one step; pulsing with pin 1 resets gain to maximum. |
| 3 | A5 | input | Attenuation bit five (16-dB step) in parallel mode; unused in serial and pulse modes and connected to DC ground. |
| 4 | MOD0 | input | Digital mode control pin that floats to logic high if unconnected; set with MOD1 to select parallel, serial or pulse mode (MOD0=0 in serial mode). |
| 5 | MOD1 | input | Digital mode control pin that floats to logic high if unconnected; set with MOD0 to select parallel, serial or pulse mode (MOD1=0 in pulse mode). |
| 6 | B5 | input | Attenuation bit five (16-dB step) for channel B in parallel mode; unused in serial and pulse modes and connected to DC ground. |
| 7 | B4/UPB | input | Parallel mode B4 is attenuation bit four (8-dB step) and pulse mode UPB is the up pulse pin (logic 0 pulse increases gain one step); pulsing with pin 8 resets gain to maximum; connect to DC ground in serial mode. |
| 8 | B3/DNB | input | Parallel mode B3 is attenuation bit three (4-dB step) and pulse mode DNB is the down pulse pin (logic 0 pulse decreases gain one step); pulsing with pin 7 resets gain to maximum; connect to DC ground in serial mode. |
| 9 | B2/S1B | input | Parallel mode B2 is attenuation bit two (2-dB step) and pulse mode S1B is step size bit 1 ((0,0)=0.5 dB, (0,1)=1 dB, (1,0)=2 dB, (1,1)=6 dB); connect to DC ground in serial mode. |
| 10 | B1/S0B | input | Parallel mode B1 is attenuation bit one (1-dB step) and pulse mode S0B is step size bit 0 ((0,0)=0.5 dB, (0,1)=1 dB, (1,0)=2 dB, (1,1)=6 dB); connect to DC ground in serial mode. |
| 11 | INB+ | input | Channel B noninverting amplifier input, internally biased to mid supply; input voltage must not exceed V+ or go below GND by more than 0.5 V. |
| 12 | INB- | input | Channel B inverting amplifier input, internally biased to mid supply; input voltage must not exceed V+ or go below GND by more than 0.5 V. |
| 13 | GND | power_in | Ground pin to connect to a low impedance ground plane; all pin voltages are specified with respect to these pins and the exposed pad is internally bonded to them. |
| 14 | +5V | power_in | Power supply pin with a valid range of 4.75 V to 5.25 V. |
| 15 | GND | power_in | Ground pin to connect to a low impedance ground plane; all pin voltages are specified with respect to these pins and the exposed pad is internally bonded to them. |
| 16 | B0 | input | Attenuation bit zero (0.5-dB step) for channel B in parallel mode, where 000000 is maximum gain; connect to DC ground in serial and pulse modes. |
| 17 | OUTB+ | output | Channel B noninverting amplifier output, externally biased to 0 V. |
| 18 | OUTB- | output | Channel B inverting amplifier output, externally biased to 0 V. |
| 19 | ENB | input | Channel B enable pin, logic 1 = enabled state; floats high if left unconnected. |
| 20 | LATB | input | Channel B latch pin in parallel mode (logic 0 = active, logic 1 = latched, gain unchanged once high); connect to ground if latch is not desired or in serial and pulse modes. |
| 21 | LATA | input | Channel A latch pin in parallel mode (logic 0 = active, logic 1 = latched, gain unchanged once high); connect to ground if latch is not desired or in serial and pulse modes. |
| 22 | ENA | input | Channel A enable pin, logic 1 = enabled state; floats high if left unconnected. |
| 23 | OUTA- | output | Channel A inverting amplifier output, externally biased to 0 V. |
| 24 | OUTA+ | output | Channel A noninverting amplifier output, externally biased to 0 V. |
| 25 | A0 | input | Attenuation bit zero (0.5-dB step) for channel A in parallel mode, where 000000 is maximum gain; connect to DC ground in pulse mode and leave NC in serial mode per Table 1. |
| 26 | GND | power_in | Ground pin to connect to a low impedance ground plane; all pin voltages are specified with respect to these pins and the exposed pad is internally bonded to them. |
| 27 | +5V | power_in | Power supply pin with a valid range of 4.75 V to 5.25 V. |
| 28 | GND | power_in | Ground pin to connect to a low impedance ground plane; all pin voltages are specified with respect to these pins and the exposed pad is internally bonded to them. |
| 29 | INA- | input | Channel A inverting amplifier input, internally biased to mid supply; input voltage must not exceed V+ or go below GND by more than 0.5 V. |
| 30 | INA+ | input | Channel A noninverting amplifier input, internally biased to mid supply; input voltage must not exceed V+ or go below GND by more than 0.5 V. |
| 31 | A1/SDO/S0A | input | Parallel mode A1 is attenuation bit one (1-dB step), serial mode SDO is serial data out (SPI), and pulse mode S0A is step size bit 0 ((0,0)=0.5 dB, (0,1)=1 dB, (1,0)=2 dB, (1,1)=6 dB). |
| 32 | A2/CS/S1A | input | Parallel mode A2 is attenuation bit two (2-dB step), serial mode CS is the active-low chip select (SPI), and pulse mode S1A is step size bit 1 ((0,0)=0.5 dB, (0,1)=1 dB, (1,0)=2 dB, (1,1)=6 dB). |
| 33 | GND | power_in | Exposed thermal pad, connect to a low impedance ground plane; it is internally bonded to the ground pins. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-32-EP(5x5) |
| Category | Operational Amplifier/Comparator |
| Pins | 33 |

## CAD (KiCad official)

- Symbol: `LMH6521SQ`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `lmh6521sq-etched.step` / `lmh6521sq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmh6521sq.step` / `lmh6521sq.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmh6521) (38 pp, sha256 `73c886f243e5aa0c`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lmh6521sq-datasheet.pdf)