LMH1297RTVT

Texas Instruments · Video Interface ICs · WQFN-32-EP(5x5)

LMH1297RTVT from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDI_IO+	bidirectional	Single-ended complementary input or output with on-chip 75-Ω termination; configurable as 75-Ω adaptive cable equalizer input in EQ mode or 75-Ω cable driver output in CD mode for SMPTE video up to 11.88 Gbps.
2	SDI_IO-	bidirectional	Single-ended complementary input or output with on-chip 75-Ω termination; configurable as 75-Ω adaptive cable equalizer input in EQ mode or 75-Ω cable driver output in CD mode for SMPTE video up to 11.88 Gbps.
3	VSS	power_in	Ground reference.
4	OUT0_SEL	input	Logic control enabling 100-Ω host-side output driver at OUT0±; internally pulled high by default to disable OUT0.
5	EQ/CD_SEL	input	Logic control selecting signal direction as adaptive equalizer (EQ mode, internally pulled low) or cable driver (CD mode) for bidirectional SDI_IO.
6	VSS	power_in	Ground reference.
7	SDI_OUT-	output	Single-ended complementary 75-Ω output with on-chip termination and return loss network; used as loop-through output in EQ mode or secondary cable driver output in CD mode.
8	SDI_OUT+	output	Single-ended complementary 75-Ω output with on-chip termination and return loss network; used as loop-through output in EQ mode or secondary cable driver output in CD mode.
9	HOST_EQ0	input	4-level control pin selecting output amplitude and de-emphasis for OUT0± in EQ mode or equalizer boost setting for IN0± in CD mode.
10	RSV1	unconnected	Reserved pin; do not connect.
11	SS_N/ADDR0	input	SPI Target Select (active low, 2.5-V LVCMOS, internally pulled high) in SPI mode or SMBus address strap (4-level) in SMBus mode.
12	MODE_SEL	input	4-level control pin selecting serial interface mode: SPI at Level F (float) or SMBus at Level L (1 kΩ to VSS).
13	MOSI/SDA	input	SPI Master Output Slave Input (2.5-V LVCMOS input) in SPI mode or SMBus bidirectional data line (3.3-V tolerant, open-drain) in SMBus mode; external pullup recommended in SPI mode.
14	SDI_OUT_SEL	input	Logic control enabling 75-Ω output driver at SDI_OUT±; internally pulled high by default to disable SDI_OUT.
15	RSV2	unconnected	Reserved pin; do not connect.
16	RSV3	unconnected	Reserved pin; do not connect.
17	OUT_CTRL	input	4-level control pin selecting output signal routing and enabling or bypassing reclocker and cable equalizer.
18	IN0-	input	Differential input from host video processor with on-chip 100-Ω differential termination; requires external 4.7-µF AC-coupling capacitors for SMPTE applications.
19	IN0+	input	Differential input from host video processor with on-chip 100-Ω differential termination; requires external 4.7-µF AC-coupling capacitors for SMPTE applications.
20	VSS	power_in	Ground reference.
21	VDD_CDR	power_in	2.5-V ± 5% power supply for reclocker circuitry; connect to same supply as VIN with 0.1-µF bypass capacitor.
22	OUT0-	output	Differential 100-Ω output to host video processor with on-chip differential termination; requires external 4.7-µF AC-coupling capacitors for SMPTE applications.
23	OUT0+	output	Differential 100-Ω output to host video processor with on-chip differential termination; requires external 4.7-µF AC-coupling capacitors for SMPTE applications.
24	SDI_VOD	input	4-level control pin selecting one of four output amplitudes (±5% or nominal) for cable drivers at SDI_IO± and SDI_OUT±.
25	RSV5	unconnected	Reserved pin; do not connect.
26	RSV4	unconnected	Reserved pin; do not connect.
27	LOCK_N	tri_state	3.3-V tolerant, open-drain output indicating reclocker lock (active low); can be reconfigured via register for carrier detect (CD_N) or interrupt (INT_N) indication.
28	MISO/ADDR1	output	SPI Master Input Slave Output (2.5-V LVCMOS output) in SPI mode or SMBus address strap (4-level) in SMBus mode.
29	SCK/SCL	input	SPI Serial Clock (2.5-V LVCMOS input) in SPI mode or SMBus clock line (3.3-V tolerant, open-drain, bidirectional) in SMBus mode.
30	VIN	power_in	2.5-V ± 5% external power supply with 10-µF and 1-µF bulk decoupling and 0.1-µF bypass capacitor.
31	VDD_LDO	power_out	Internal 1.8-V LDO regulator output for powering internal circuitry only; requires 1-µF and 0.1-µF bypass capacitors to VSS.
32	ENABLE	input	Logic control enabling normal operation (logic high) or forcing power-down mode (logic low); internally pulled high by default.
EP	Exposed Pad	power_in	Thermal and ground connection at package bottom; connect to VSS plane through 3 × 3 via array for thermal performance and mechanical robustness.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-32-EP(5x5)
Category	Interface
Pins	33

CAD (KiCad official)

Symbol: LMH1297RTVT
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: lmh1297rtvt-etched.step / lmh1297rtvt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmh1297rtvt.step / lmh1297rtvt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (53 pp, sha256 2dc0a821b809e09a, retrieved 2026-09-29, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# LMH1297RTVT

**Texas Instruments** · Video Interface ICs · WQFN-32-EP(5x5)

LMH1297RTVT from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDI_IO+ | bidirectional | Single-ended complementary input or output with on-chip 75-Ω termination; configurable as 75-Ω adaptive cable equalizer input in EQ mode or 75-Ω cable driver output in CD mode for SMPTE video up to 11.88 Gbps. |
| 2 | SDI_IO- | bidirectional | Single-ended complementary input or output with on-chip 75-Ω termination; configurable as 75-Ω adaptive cable equalizer input in EQ mode or 75-Ω cable driver output in CD mode for SMPTE video up to 11.88 Gbps. |
| 3 | VSS | power_in | Ground reference. |
| 4 | OUT0_SEL | input | Logic control enabling 100-Ω host-side output driver at OUT0±; internally pulled high by default to disable OUT0. |
| 5 | EQ/CD_SEL | input | Logic control selecting signal direction as adaptive equalizer (EQ mode, internally pulled low) or cable driver (CD mode) for bidirectional SDI_IO. |
| 6 | VSS | power_in | Ground reference. |
| 7 | SDI_OUT- | output | Single-ended complementary 75-Ω output with on-chip termination and return loss network; used as loop-through output in EQ mode or secondary cable driver output in CD mode. |
| 8 | SDI_OUT+ | output | Single-ended complementary 75-Ω output with on-chip termination and return loss network; used as loop-through output in EQ mode or secondary cable driver output in CD mode. |
| 9 | HOST_EQ0 | input | 4-level control pin selecting output amplitude and de-emphasis for OUT0± in EQ mode or equalizer boost setting for IN0± in CD mode. |
| 10 | RSV1 | unconnected | Reserved pin; do not connect. |
| 11 | SS_N/ADDR0 | input | SPI Target Select (active low, 2.5-V LVCMOS, internally pulled high) in SPI mode or SMBus address strap (4-level) in SMBus mode. |
| 12 | MODE_SEL | input | 4-level control pin selecting serial interface mode: SPI at Level F (float) or SMBus at Level L (1 kΩ to VSS). |
| 13 | MOSI/SDA | input | SPI Master Output Slave Input (2.5-V LVCMOS input) in SPI mode or SMBus bidirectional data line (3.3-V tolerant, open-drain) in SMBus mode; external pullup recommended in SPI mode. |
| 14 | SDI_OUT_SEL | input | Logic control enabling 75-Ω output driver at SDI_OUT±; internally pulled high by default to disable SDI_OUT. |
| 15 | RSV2 | unconnected | Reserved pin; do not connect. |
| 16 | RSV3 | unconnected | Reserved pin; do not connect. |
| 17 | OUT_CTRL | input | 4-level control pin selecting output signal routing and enabling or bypassing reclocker and cable equalizer. |
| 18 | IN0- | input | Differential input from host video processor with on-chip 100-Ω differential termination; requires external 4.7-µF AC-coupling capacitors for SMPTE applications. |
| 19 | IN0+ | input | Differential input from host video processor with on-chip 100-Ω differential termination; requires external 4.7-µF AC-coupling capacitors for SMPTE applications. |
| 20 | VSS | power_in | Ground reference. |
| 21 | VDD_CDR | power_in | 2.5-V ± 5% power supply for reclocker circuitry; connect to same supply as VIN with 0.1-µF bypass capacitor. |
| 22 | OUT0- | output | Differential 100-Ω output to host video processor with on-chip differential termination; requires external 4.7-µF AC-coupling capacitors for SMPTE applications. |
| 23 | OUT0+ | output | Differential 100-Ω output to host video processor with on-chip differential termination; requires external 4.7-µF AC-coupling capacitors for SMPTE applications. |
| 24 | SDI_VOD | input | 4-level control pin selecting one of four output amplitudes (±5% or nominal) for cable drivers at SDI_IO± and SDI_OUT±. |
| 25 | RSV5 | unconnected | Reserved pin; do not connect. |
| 26 | RSV4 | unconnected | Reserved pin; do not connect. |
| 27 | LOCK_N | tri_state | 3.3-V tolerant, open-drain output indicating reclocker lock (active low); can be reconfigured via register for carrier detect (CD_N) or interrupt (INT_N) indication. |
| 28 | MISO/ADDR1 | output | SPI Master Input Slave Output (2.5-V LVCMOS output) in SPI mode or SMBus address strap (4-level) in SMBus mode. |
| 29 | SCK/SCL | input | SPI Serial Clock (2.5-V LVCMOS input) in SPI mode or SMBus clock line (3.3-V tolerant, open-drain, bidirectional) in SMBus mode. |
| 30 | VIN | power_in | 2.5-V ± 5% external power supply with 10-µF and 1-µF bulk decoupling and 0.1-µF bypass capacitor. |
| 31 | VDD_LDO | power_out | Internal 1.8-V LDO regulator output for powering internal circuitry only; requires 1-µF and 0.1-µF bypass capacitors to VSS. |
| 32 | ENABLE | input | Logic control enabling normal operation (logic high) or forcing power-down mode (logic low); internally pulled high by default. |
| EP | Exposed Pad | power_in | Thermal and ground connection at package bottom; connect to VSS plane through 3 × 3 via array for thermal performance and mechanical robustness. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-32-EP(5x5) |
| Category | Interface |
| Pins | 33 |

## CAD (KiCad official)

- Symbol: `LMH1297RTVT`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `lmh1297rtvt-etched.step` / `lmh1297rtvt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmh1297rtvt.step` / `lmh1297rtvt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmh1297) (53 pp, sha256 `2dc0a821b809e09a`, retrieved 2026-09-29, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lmh1297rtvt-datasheet.pdf)