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LMH1208RTVT
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Texas Instruments Video Interface ICs, WQFN-32-EP(5x5). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# LMH1208RTVT++**Texas Instruments** · Video Interface ICs · WQFN-32-EP(5x5)++LMH1208RTVT from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SDI_OUT1+ | output | Single-ended complementary output to 75-Ω cable with integrated on-chip 75-Ω termination and return loss compensation network; requires 4.7-µF AC-coupling capacitor. |+| 2 | SDI_OUT1- | output | Single-ended complementary return output to 75-Ω cable with integrated on-chip 75-Ω termination; requires 4.7-µF AC-coupling capacitor and external 75-Ω termination to GND. |+| 3 | VSS | power_in | Ground reference. |+| 4 | OUT0_SEL | input | LVCMOS control pin to enable 100-Ω host-side output driver at OUT0±; internally pulled high by default (OUT0 disabled). |+| 5 | RSV6 | unconnected | Reserved pin; do not connect. |+| 6 | VSS | power_in | Ground reference. |+| 7 | SDI_OUT2- | output | Single-ended complementary return output to 75-Ω cable with integrated on-chip 75-Ω termination; requires 4.7-µF AC-coupling capacitor and external 75-Ω termination to GND. |+| 8 | SDI_OUT2+ | output | Single-ended complementary output to 75-Ω cable with integrated on-chip 75-Ω termination and return loss compensation; requires 4.7-µF AC-coupling capacitor. |+| 9 | HOST_EQ0 | input | 4-level strap pin; selects equalizer setting for IN0± differential input (H/F/R/L correspond to EQ boost levels 0x00/0x00/0x80/0x90). |+| 10 | RSV1 | unconnected | Reserved pin; do not connect. |+| 11 | SS_N | input | SPI slave select (active low) LVCMOS input when MODE_SEL = F; also serves as ADDR0 4-level SMBus address strap when MODE_SEL = L; internally pulled high by default. |+| 12 | MODE_SEL | input | 4-level strap pin; selects SPI interface (F) or SMBus interface (L) for serial control access. |+| 13 | MOSI | input | SPI master output/slave input (2.5-V LVCMOS) when MODE_SEL = F; also serves as SDA SMBus bidirectional data line (open-drain, 3.3-V tolerant) when MODE_SEL = L. |+| 14 | SDI_OUT2_SEL | input | LVCMOS control pin to enable 75-Ω cable driver output at SDI_OUT2±; internally pulled high by default (SDI_OUT2 disabled). |+| 15 | RSV2 | unconnected | Reserved pin; do not connect. |+| 16 | RSV3 | unconnected | Reserved pin; do not connect. |+| 17 | SLEW_CTRL | input | 4-level strap pin; selects output edge rate and pre-emphasis level for cable drivers SDI_OUT1± and SDI_OUT2± based on SMPTE data rate (H/F/R/L for 12G/HD/270M rates). |+| 18 | IN0- | input | Differential input from host video processor to 100-Ω on-chip termination; requires 4.7-µF AC-coupling capacitor. |+| 19 | IN0+ | input | Differential input from host video processor to 100-Ω on-chip termination; requires 4.7-µF AC-coupling capacitor. |+| 20 | VSS | power_in | Ground reference. |+| 21 | RSV_L | power_in | Power supply input; connect to same 2.5-V ± 5% external supply as VIN. |+| 22 | OUT0- | output | Differential output to host video processor from 100-Ω driver with on-chip termination; requires 4.7-µF AC-coupling capacitor. |+| 23 | OUT0+ | output | Differential output to host video processor from 100-Ω driver with on-chip termination; requires 4.7-µF AC-coupling capacitor. |+| 24 | SDI_VOD | input | 4-level strap pin; selects output amplitude for cable drivers SDI_OUT1± and SDI_OUT2± (H/F/R/L correspond to +5%/800mVpp/+10%/-5% of nominal). |+| 25 | RSV5 | unconnected | Reserved pin; do not connect. |+| 26 | RSV4 | unconnected | Reserved pin; do not connect. |+| 27 | SD_N | output | Signal detect indicator; 3.3-V tolerant open-drain output that pulls low when signal is detected at IN0±; requires external resistor to logic supply. |+| 28 | MISO | output | SPI master input/slave output (2.5-V LVCMOS) when MODE_SEL = F; also serves as ADDR1 4-level SMBus address strap when MODE_SEL = L. |+| 29 | SCK | input | SPI serial clock input (2.5-V LVCMOS) when MODE_SEL = F; also serves as SCL SMBus clock line (open-drain, 3.3-V tolerant) when MODE_SEL = L. |+| 30 | VIN | power_in | Main power supply input; connect to external 2.5-V ± 5% supply. |+| 31 | VDD_LDO | power_out | Output of internal 1.8-V LDO regulator for internal circuitry; requires external 1-µF and 0.1-µF bypass capacitors to VSS. |+| 32 | ENABLE | input | LVCMOS control pin; logic high enables normal operation, logic low forces power-down mode; internally pulled high by default. |+| EP | EP | power_in | Exposed thermal pad at bottom of package; connect to VSS ground plane through 3×3 via array for thermal and mechanical performance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-32-EP(5x5) |+| Category | Interface |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `LMH1208RTVT`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `lmh1208rtvt-etched.step` / `lmh1208rtvt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lmh1208rtvt.step` / `lmh1208rtvt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lmh1208) (48 pp, sha256 `ec37be72aa001a79`, retrieved 2026-09-29, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lmh1208rtvt-datasheet.pdf)
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Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "lmh1208rtvt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lmh1208rtvt.kicad_sym",+ "lmh1208rtvt.kicad_mod",+ "lmh1208rtvt.glb",+ "lmh1208rtvt.step",+ "lmh1208rtvt.lbr",+ "docs/hero.png",+ "docs/lmh1208rtvt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "LMH1208RTVT",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Interface",+ "subcategory": "Video Interface ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lmh1208",+ "parts": {+ "symbol": "lmh1208rtvt.kicad_sym",+ "footprint": "lmh1208rtvt.kicad_mod",+ "model_3d": "lmh1208rtvt-etched.glb",+ "model_3d_plain": "lmh1208rtvt.glb",+ "model_3d_step": "lmh1208rtvt-etched.step",+ "model_3d_step_plain": "lmh1208rtvt.step",+ "lbr": "lmh1208rtvt.lbr"+ },+ "distributor_links": {+ "lcsc": "C2652837",+ "digikey": "296-51329-2-ND",+ "mouser": "595-LMH1208RTVT"+ },+ "distributor_check": {+ "checked_at": "2026-09-29T16:42:17Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-51329-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-LMH1208RTVT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SDI_OUT1+",+ "type": "output",+ "description": "Single-ended complementary output to 75-Ω cable with integrated on-chip 75-Ω termination and return loss compensation network; requires 4.7-µF AC-coupling capacitor."+ },+ {+ "number": "2",+ "name": "SDI_OUT1-",+ "type": "output",+ "description": "Single-ended complementary return output to 75-Ω cable with integrated on-chip 75-Ω termination; requires 4.7-µF AC-coupling capacitor and external 75-Ω termination to GND."+ },+ {+ "number": "3",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "4",+ "name": "OUT0_SEL",+ "type": "input",+ "description": "LVCMOS control pin to enable 100-Ω host-side output driver at OUT0±; internally pulled high by default (OUT0 disabled)."+ },+ {+ "number": "5",+ "name": "RSV6",+ "type": "unconnected",+ "description": "Reserved pin; do not connect."+ },+ {+ "number": "6",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "7",+ "name": "SDI_OUT2-",+ "type": "output",+ "description": "Single-ended complementary return output to 75-Ω cable with integrated on-chip 75-Ω termination; requires 4.7-µF AC-coupling capacitor and external 75-Ω termination to GND."+ },+ {+ "number": "8",+ "name": "SDI_OUT2+",+ "type": "output",+ "description": "Single-ended complementary output to 75-Ω cable with integrated on-chip 75-Ω termination and return loss compensation; requires 4.7-µF AC-coupling capacitor."+ },+ {+ "number": "9",+ "name": "HOST_EQ0",+ "type": "input",+ "description": "4-level strap pin; selects equalizer setting for IN0± differential input (H/F/R/L correspond to EQ boost levels 0x00/0x00/0x80/0x90)."+ },+ {+ "number": "10",+ "name": "RSV1",+ "type": "unconnected",+ "description": "Reserved pin; do not connect."+ },+ {+ "number": "11",+ "name": "SS_N",+ "type": "input",+ "description": "SPI slave select (active low) LVCMOS input when MODE_SEL = F; also serves as ADDR0 4-level SMBus address strap when MODE_SEL = L; internally pulled high by default."+ },+ {+ "number": "12",+ "name": "MODE_SEL",+ "type": "input",+ "description": "4-level strap pin; selects SPI interface (F) or SMBus interface (L) for serial control access."+ },+ {+ "number": "13",+ "name": "MOSI",+ "type": "input",+ "description": "SPI master output/slave input (2.5-V LVCMOS) when MODE_SEL = F; also serves as SDA SMBus bidirectional data line (open-drain, 3.3-V tolerant) when MODE_SEL = L."+ },+ {+ "number": "14",+ "name": "SDI_OUT2_SEL",+ "type": "input",+ "description": "LVCMOS control pin to enable 75-Ω cable driver output at SDI_OUT2±; internally pulled high by default (SDI_OUT2 disabled)."+ },+ {+ "number": "15",+ "name": "RSV2",+ "type": "unconnected",+ "description": "Reserved pin; do not connect."+ },+ {+ "number": "16",+ "name": "RSV3",+ "type": "unconnected",+ "description": "Reserved pin; do not connect."+ },+ {+ "number": "17",+ "name": "SLEW_CTRL",+ "type": "input",+ "description": "4-level strap pin; selects output edge rate and pre-emphasis level for cable drivers SDI_OUT1± and SDI_OUT2± based on SMPTE data rate (H/F/R/L for 12G/HD/270M rates)."+ },+ {+ "number": "18",+ "name": "IN0-",+ "type": "input",+ "description": "Differential input from host video processor to 100-Ω on-chip termination; requires 4.7-µF AC-coupling capacitor."+ },+ {+ "number": "19",+ "name": "IN0+",+ "type": "input",+ "description": "Differential input from host video processor to 100-Ω on-chip termination; requires 4.7-µF AC-coupling capacitor."+ },+ {+ "number": "20",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "21",+ "name": "RSV_L",+ "type": "power_in",+ "description": "Power supply input; connect to same 2.5-V ± 5% external supply as VIN."+ },+ {+ "number": "22",+ "name": "OUT0-",+ "type": "output",+ "description": "Differential output to host video processor from 100-Ω driver with on-chip termination; requires 4.7-µF AC-coupling capacitor."+ },+ {+ "number": "23",+ "name": "OUT0+",+ "type": "output",+ "description": "Differential output to host video processor from 100-Ω driver with on-chip termination; requires 4.7-µF AC-coupling capacitor."+ },+ {+ "number": "24",+ "name": "SDI_VOD",+ "type": "input",+ "description": "4-level strap pin; selects output amplitude for cable drivers SDI_OUT1± and SDI_OUT2± (H/F/R/L correspond to +5%/800mVpp/+10%/-5% of nominal)."+ },+ {+ "number": "25",+ "name": "RSV5",+ "type": "unconnected",+ "description": "Reserved pin; do not connect."+ },+ {+ "number": "26",+ "name": "RSV4",+ "type": "unconnected",+ "description": "Reserved pin; do not connect."+ },+ {+ "number": "27",+ "name": "SD_N",+ "type": "output",+ "description": "Signal detect indicator; 3.3-V tolerant open-drain output that pulls low when signal is detected at IN0±; requires external resistor to logic supply."+ },+ {+ "number": "28",+ "name": "MISO",+ "type": "output",+ "description": "SPI master input/slave output (2.5-V LVCMOS) when MODE_SEL = F; also serves as ADDR1 4-level SMBus address strap when MODE_SEL = L."+ },+ {+ "number": "29",+ "name": "SCK",+ "type": "input",+ "description": "SPI serial clock input (2.5-V LVCMOS) when MODE_SEL = F; also serves as SCL SMBus clock line (open-drain, 3.3-V tolerant) when MODE_SEL = L."+ },+ {+ "number": "30",+ "name": "VIN",+ "type": "power_in",+ "description": "Main power supply input; connect to external 2.5-V ± 5% supply."+ },+ {+ "number": "31",+ "name": "VDD_LDO",+ "type": "power_out",+ "description": "Output of internal 1.8-V LDO regulator for internal circuitry; requires external 1-µF and 0.1-µF bypass capacitors to VSS."+ },+ {+ "number": "32",+ "name": "ENABLE",+ "type": "input",+ "description": "LVCMOS control pin; logic high enables normal operation, logic low forces power-down mode; internally pulled high by default."+ },+ {+ "number": "EP",+ "name": "EP",+ "type": "power_in",+ "description": "Exposed thermal pad at bottom of package; connect to VSS ground plane through 3×3 via array for thermal and mechanical performance."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lmh1208",+ "pages": 48,+ "sha256": "ec37be72aa001a79",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}