component

LMH0395SQ

Public Made by Adom

by adom

Texas Instruments Video Interface ICs, WQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232lmh0395sqfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

LMH0395SQ

Texas Instruments · Video Interface ICs · WQFN-24-EP(4x4)

LMH0395SQ from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VEE power_in Negative power supply (ground); all device voltages are referenced to VEE = 0 V.
2 VEE power_in Negative power supply (ground); all device voltages are referenced to VEE = 0 V.
3 SDI input Serial data true input, analog; common-mode range 1.65 V (VCMIN) with 720-880 mVP-P input swing at 0 m cable length.
4 SDI input Serial data complement input, analog; differential partner of pin 3.
5 VEE power_in Negative power supply (ground); all device voltages are referenced to VEE = 0 V.
6 SPI_EN input SPI register access enable (LVCMOS, internal pulldown); H selects SPI register access mode and L selects pin mode.
7 SDO1_DISABLE input Output driver 1 (SDO1, SDO1) disable (LVCMOS, internal pullup); H or no connection puts the driver in high-impedance state and L enables it.
8 AEC+ bidirectional AEC loop filter external capacitor (1-µF) positive connection; the capacitor is optional.
9 AEC- bidirectional AEC loop filter external capacitor (1-µF) negative connection; the capacitor is optional.
10 CD output Carrier detect (LVCMOS); H indicates no input signal detected and L indicates input signal detected.
11 MUTEREF input Mute reference input (analog) that sets the CD threshold and the maximum cable length equalized before muting; may be unconnected or connected to ground for normal CD operation.
12 VEE power_in Negative power supply (ground); all device voltages are referenced to VEE = 0 V.
13 SS (SPI) input SPI slave select (LVCMOS, internal pullup).
14 SDO0 output Serial data output 0 complement, LVDS; differential partner of pin 15.
15 SDO0 output Serial data output 0 true, LVDS; internally terminated 100-Ω LVDS output.
16 VEE power_in Negative power supply (ground); all device voltages are referenced to VEE = 0 V.
17 SDO1 output Serial data output 1 complement, LVDS; differential partner of pin 18.
18 SDO1 output Serial data output 1 true, LVDS; internally terminated 100-Ω LVDS output.
19 MISO (SPI) output SPI Master Input / Slave Output (LVCMOS); carries LMH0395 control data transmit.
20 VCC power_in Positive power supply, +2.5 V nominal (VCC - VEE supply range 2.375 V to 2.625 V).
21 SCK (SPI) input SPI serial clock input (LVCMOS).
22 MOSI (SPI) input SPI Master Output / Slave Input (LVCMOS, internal pulldown); carries LMH0395 control data receive.
23 VEE power_in Negative power supply (ground); all device voltages are referenced to VEE = 0 V.
24 VCC power_in Positive power supply, +2.5 V nominal (VCC - VEE supply range 2.375 V to 2.625 V).
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-24-EP(4x4)
Category Communication Interface Chip/UART/485/232
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage 3.1 V 6
Input voltage (all inputs) -0.3 V 6
Junction temperature 125 °C 6
Storage temperature Tstg -65 150 °C 6
Supply voltage VCC, VEE 2.375 2.5 2.625 V 6
Operating free-air temperature TA -40 25 85 °C 6
Input voltage high level VIH 1.7 V Logic Inputs 6
Input voltage low level VIL 0.7 V Logic Inputs 6
Input voltage swing VSDI 720 800 880 mVP−P 0-m cable length 6
Input common-mode voltage VCMIN 1.65 V SDI or SDI 6
Differential output voltage, P-P VSSP-P 500 700 900 mVP-P SDO0, SDO0, SDO1, SDO1 (100-Ω load), default register settings, Figure 1 7
Differential output voltage VOD 250 350 450 mV 7
Change in magnitude of VOD for complementary output states ΔVOD 50 mV 7
Offset voltage VOS 1.1 1.2 1.35 V 7
Change in magnitude of VOS for complementary output states ΔVOS 50 mV 7
Output short circuit current IOS 30 mA 7
Output voltage high level VOH 2 V CD, MISO, IOH = -2 mA 7
Output voltage low level VOL 0.2 V CD, MISO, IOL = +2 mA 7
Supply current, normal operation dual outputs ICC 55 78 mA Normal operation, dual outputs 7
Supply current, normal operation single output ICC 45 65 mA Normal operation, single output 7
Supply current, power-save mode ICC 7 10 mA Power-save mode 7
Minimum input data rate BRMIN 125 Mbps SDI, SDI 7
Maximum input data rate BRMAX 2970 Mbps SDI, SDI 7
Jitter for various cable lengths TJRAW 0.2 UI 2.97 Gbps, Belden 1694A, 0-100 meters 7
Jitter for various cable lengths TJRAW 0.3 UI 2.97 Gbps, Belden 1694A, 100-140 meters 7
Jitter for various cable lengths TJRAW 0.5 UI 2.97 Gbps, Belden 1694A, 140-180 meters 7
Jitter for various cable lengths TJRAW 0.55 UI 2.97 Gbps, Belden 1694A, 180-200 meters 7
Output rise time, fall time tr, tf 90 130 ps 20%, 80%, 100-Ω load, Figure 1 7
Mismatch in rise/fall time ΔTR-F 2 15 ps 7
Output overshoot tOS 1 5 % 7
Input return loss RLIN 15 dB 5 MHz - 1.5 GHz 8
Input return loss RLIN 10 dB 1.5 GHz - 3.0 GHz 8
MISO driven-to-tristate time tODZ 20 ns MISO, see Figure 3 8
MISO tristate-to-driven time tOZD 10 ns MISO, see Figure 3 8
MISO output delay time tOD 15 ns MISO, see Figure 3 8
Frequency SCK fSCK 20 MHz 8
SCK pulse width high tPH 40 % SCK period SCK, see Figure 2, Figure 3 8
SCK pulse width low tPL 40 % SCK period SCK, see Figure 2, Figure 3 8
MOSI set-up time tSU 4 ns MOSI, see Figure 2, Figure 3 8
MOSI hold time tH 4 ns 8
SS set-up time tSSSU 14 ns SS, see Figure 2, Figure 3 8
SS hold time tSSH 4 ns 8
SS OFF-time tSSOF 1 SCK period 8
Input resistance RIN 1.5 kΩ Single-ended, SDI, SDI 8
Input capacitance CIN 0.7 pF Single-ended, SDI, SDI 8
MUTEREF DC voltage (floating) MUTEREF 1.3 V floating 7
MUTEREF range MUTERNG 0.8 V 7
Junction-to-ambient thermal resistance RθJA 40 °C/W RTW (WQFN) 24 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 6 °C/W RTW (WQFN) 24 pins 6

CAD (KiCad official)

  • Symbol: LMH0395SQ
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: lmh0395sq-etched.step / lmh0395sq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmh0395sq.step / lmh0395sq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 ff3b9251d9d0c86a, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF