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LM96080CIMTX

Public Made by Adom

by adom

Texas Instruments Monitors & Reset Circuits, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM96080CIMTX

Texas Instruments · Monitors & Reset Circuits · TSSOP-24

LM96080CIMTX from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INT_IN input Active-low interrupt input that propagates the INT_IN signal to the INT output of the LM96080.
2 SDA bidirectional Serial bus bidirectional data pin with NMOS open-drain output.
3 SCL input Serial bus clock input.
4 FAN1 input Fan tachometer input 1.
5 FAN2 input Fan tachometer input 2.
6 BTI input Board Temperature Interrupt input driven by the O.S. outputs of additional temperature sensors such as LM75, with an internal 10 kΩ pull-up.
7 GPI (CI) bidirectional General purpose input usable as an additional active-high interrupt input or as an input from an external circuit latching a Chassis Intrusion event.
8 GND power_in Ground, internally connected to all of the digital circuitry.
9 V+ power_in +3.0V to +5.5V power supply, bypassed with 10 μF (electrolytic or tantalum) in parallel with 0.1 μF (ceramic) capacitors.
10 INT output Interrupt output, non-maskable active-high PMOS open-drain or active-low NMOS open-drain interrupt request, active whenever INT_IN, BTI, or GPI interrupts.
11 GPO output General purpose active-low NMOS open-drain output intended to drive an external power PMOS for software power control or to control power to a cooling fan.
12 NTEST_IN/RESET_IN input Active-low input that enables NAND Tree board-level connectivity testing, and the LM96080 resets to its power-on state whenever NAND Tree connectivity is enabled.
13 RST_OUT/OS output NMOS open-drain output where RST_OUT provides a master reset to connected devices and OS is dedicated to the temperature reading WATCHDOG.
14 GNDA power_in Analog ground, internally connected to all analog circuitry and the reference for all analog inputs; must be taken to a low-noise analog ground plane.
15 IN6 input Analog input with 0V to 2.56V full-scale range.
16 IN5 input Analog input with 0V to 2.56V full-scale range.
17 IN4 input Analog input with 0V to 2.56V full-scale range.
18 IN3 input Analog input with 0V to 2.56V full-scale range.
19 IN2 input Analog input with 0V to 2.56V full-scale range.
20 IN1 input Analog input with 0V to 2.56V full-scale range.
21 IN0 input Analog input with 0V to 2.56V full-scale range.
22 A0/NTEST_OUT bidirectional Lowest order bit of the serial bus address, which also functions as an output during a NAND Tree test.
23 A1 input One of the two highest order bits of the serial bus address.
24 A2 input One of the two highest order bits of the serial bus address.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Power Supply Chip
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage V+ 6 V 6
Voltage on SCL, SDA, RST_OUT/OS, GPI(CI), GPO, NTEST_IN/RESET_IN, INT_IN, FAN1, FAN2 -0.3 6 V 6
Voltage on Other Pins -0.3 6 V (−0.3)V to (V+ + 0.3V) and ≤ 6.0V 6
GND - GNDA -300 300 mV 6
Input Current at Any Pin -5 5 mA 6
Package Input Current -30 30 mA 6
Maximum Junction Temperature TJ max 150 °C 6
ESD Susceptibility Human Body Model 3000 V Human Body Model 6
ESD Susceptibility Machine Model 300 V Machine Model 6
ESD Susceptibility Charged Device Model 1000 V Charged Device Model 6
Storage Temperature -65 150 °C 6
Supply Voltage V+ 3 5.5 V 6
Voltage on SCL, SDA, RST_OUT/OS, GPI(CI), GPO, NTEST_IN/RESET_IN, INT_IN, FAN1, FAN2 -0.05 5.5 V 6
Voltage on Other Pins -0.05 5.5 V (−0.05)V to (V+ + 0.05)V and ≤ 5.5V 6
/GND − GNDA/ 100 mV 6
VIN Voltage Range VIN -0.05 V (−0.05)V to (V+ + 0.05)V 6
Operating Temperature Range TA -40 125 °C 6
Junction to Ambient Thermal Resistance θJA 95 °C/W Package Number: PW 6
Supply Voltage V+ 3 5.5 V 7
Supply Current, round robin I+ 0.43 0.58 mA Round robin conversion, V+= 5.5V 7
Supply Current, round robin I+ 0.37 0.52 mA Round robin conversion, V+= 3.8V 7
Supply Current, shutdown I+ 0.4 0.54 mA Shutdown mode, V+= 5.5V 7
Supply Current, shutdown I+ 0.33 0.48 mA Shutdown mode, V+= 3.8V 7
Temperature Error -3 3 °C (−40)°C ≤ TA ≤ +125°C 7
Temperature Error -2 2 °C (−25)°C ≤ TA ≤ +100°C 7
Temperature Resolution 0.0625 °C 7
ADC Resolution n 2.5 mV 10 bits with full-scale at 2.56V 7
Total Unadjusted Error TUE -1 1 % See(4) 7
Differential Non-Linearity DNL -1 1 LSb See(5) 7
Total Monitoring Cycle Time tC 662 728 810 ms See(6) 7
On Resistance RON 2 10 kΩ 7
Fan RPM Error -10 10 % (-40)°C ≤ TA ≤ +125°C 7
Internal Clock Frequency 20.2 22.5 24.8 kHz (-40)°C ≤ TA ≤ +125°C 7
Fan Full-scale Count 255 7
Logical 1 Output Voltage (A0/NTEST_OUT, INT) VOUT(1) 2.4 V IOUT = +5.0 mA at V+ = +4.5V, IOUT = +3.0 mA at V+ = +3.0V 7
Logical 0 Output Voltage (A0/NTEST_OUT, INT) VOUT(0) 0.4 V IOUT = +5.0 mA at V+ = +4.5V, IOUT = +3.0 mA at V+ = +3.0V 7
Logical 0 Output Voltage (open drain GPO, RST_OUT/OS, GPI(CI)) VOUT(0) 0.4 V IOUT = +5.0 mA at V+ = +4.5V, IOUT = +3.0 mA at V+ = +3.0V 8
High Level Output Current (open drain) IOH 0.005 1 μA VOUT = V+ 8
RST_OUT/OS, GPI(CI) Pulse Width 10 22.5 ms 8
Logical 0 Output Voltage (SDA) VOUT(0) 0.4 V IOUT = +3.0 mA at V+ = +3.0V 8
High Level Output Current (SDA) IOH 0.005 1 μA VOUT = V+ 8
Logical 1 Input Voltage (digital inputs) VIN(1) 2 V 8
Logical 0 Input Voltage (digital inputs) VIN(0) 0.8 V 8
Logical 1 Input Current (all digital inputs except BTI) IIN(1) -1 -0.005 μA VIN = V+ 8
Logical 0 Input Current (all digital inputs except BTI) IIN(0) 0.005 1 μA VIN = 0 VDC 8
BTI Logical 1 Input Current IIN(1) -10 -1 μA VIN = V+ 8
BTI Logical 0 Input Current IIN(0) 1 2 mA VIN = 0 VDC, V+= +5.5 V 8
SCL (Clock) Period t1 2.5 100 μs 9
Data In Setup Time to SCL High t2 100 ns 9
Data Out Stable After SCL Low t3 0 ns 9
SDA Low Setup Time to SCL Low (start) t4 100 ns 9
SDA High Hold Time After SCL High (stop) t5 100 ns 9
SCL or SDA time low for I2C bus reset tTIMEOUT 25 35 ms 9

CAD (KiCad official)

  • Symbol: LM96080CIMTX
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: lm96080cimtx-etched.step / lm96080cimtx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm96080cimtx.step / lm96080cimtx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 605076ce124409e1, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF