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LM63635DQPWPRQ1

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Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM63635DQPWPRQ1

Texas Instruments · DC-DC Converters · HTSSOP-16-EP

LM63635DQPWPRQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW power_out Regulator switch node, connected to the power inductor.
2 SW power_out Regulator switch node, connected to the power inductor (second SW pin, same net as pin 1).
3 CBOOT passive Bootstrap supply voltage for the internal high-side driver; connect a 220 nF high-quality capacitor between this pin and SW.
4 VCC power_out Internal 5 V LDO output powering the internal control circuitry; do not load externally, connect a 1 µF high-quality capacitor between VCC and PGND, usable as logic supply for the regulator functions.
5 RT input Frequency programming input: connect to VCC for 400 kHz, to AGND for 2.1 MHz, or to an RT timing resistor to AGND; must not be left floating.
6 VSEL input Output voltage selection input: VCC for 5 V, AGND for 3.3 V, or 10 kΩ to AGND for adjustable output; must not be left floating.
7 SYNC/MODE input Mode selection and synchronization input: VCC for FPWM, AGND for auto mode, or an external synchronization clock.
8 RESET output Open-drain power-good flag output (high = power good, low = power bad), pulled up through a current-limiting resistor to a suitable supply; pulled low when EN is low; may be left open if unused.
9 FB input Feedback input to the regulator: connect to the output capacitor for fixed 5 V or 3.3 V, or to the feedback divider tap for adjustable output; do not float or ground.
10 AGND power_in Analog ground and ground reference for internal reference and logic; all electrical parameters are measured to this pin; connect to system ground on the PCB.
11 EN input Regulator enable input (high = on, low = off); can be connected directly to VIN; must not be left floating.
12 VIN power_in Input supply to the regulator (3.5 V to 36 V recommended); connect a high-quality bypass capacitor directly between this pin and PGND.
13 VIN power_in Input supply to the regulator (second VIN pin, same net as pin 12); bypass directly to PGND.
14 NC unconnected No internal connection to the device circuitry.
15 PGND power_in Power ground terminal; connect to system ground and AGND, with short wide traces to the bypass capacitors.
16 PGND power_in Power ground terminal (second PGND pin, same net as pin 15); connect to system ground and AGND.
17 DAP power_in Exposed PowerPAD providing electrical ground and heat-sink connection; solder directly to the system ground plane.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Power Supply Chip
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN to PGND (HTSSOP) VIN -0.3 40 V HTSSOP package 6
EN to AGND (HTSSOP) EN -0.3 40 V HTSSOP package 6
SYNC/MODE to AGND SYNC/MODE -0.3 6 V 6
VOUT_SEL and RT to AGND -0.3 5.5 V 6
RESET to AGND RESET -0.3 16 V 6
FB to AGND (fixed VOUT mode) FB -0.3 16 V Fixed VOUT mode 6
FB to AGND (adjustable VOUT mode) FB -0.3 5.5 V Adjustable VOUT mode 6
AGND to PGND -0.3 0.3 V 6
SW to PGND (HTSSOP) SW -6 40 V Transient less than 10 ns, HTSSOP package 6
BOOT to SW -0.3 5.5 V 6
VCC to AGND VCC -0.3 5.5 V 6
Junction temperature TJ -40 150 °C 6
Storage temperature Tstg -65 150 °C 6
VIN to PGND VIN 3.5 36 V TJ -40°C to 150°C 6
EN EN 0 36 V 6
SYNC/MODE to AGND SYNC/MODE 0 5 V 6
RESET RESET 0 5 V 6
VOUT VOUT 1 20 V 6
VCC VCC 2.7 5.25 V 6
Junction-to-ambient thermal resistance RθJA 43.1 °C/W HTSSOP (PWP) 16-pin 7
Junction-to-case (top) thermal resistance RθJC(top) 35.4 °C/W HTSSOP (PWP) 16-pin 7
Junction-to-board thermal resistance RθJB 18.5 °C/W HTSSOP (PWP) 16-pin 7
Junction-to-top characterization parameter ΨJT 0.9 °C/W HTSSOP (PWP) 16-pin 7
Junction-to-board characterization parameter ΨJB 18.5 °C/W HTSSOP (PWP) 16-pin 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 4.5 °C/W HTSSOP (PWP) 16-pin 7
Non-switching input current IQ 23 40 µA VEN = 3.3V, VFB = 1.2× regulation value 8
Shutdown quiescent current ISD 5.3 10 µA VEN = 0 8
Pull-down current at SW on OVP IPOR 0.5 1.5 2.5 mA VEN = 0V, VSW = 5V 8
Precision enable high level VEN-H 1.425 1.5 1.575 V VEN rising 8
Enable input leakage current ILKG-EN -100 0.2 150 nA VEN = 13.5V, HTSSOP package 8
Resistor range for adjustable output voltage selection RSEL-ADJ 8 50 kΩ 8
Internal VCC voltage VCC 4.75 5 5.25 V 6V ≤ VIN ≤ max operating VIN 8
VCC clamp voltage VCCM 5.25 5.55 5.8 V 1mA supplied to VCC 8
Feedback voltage (adjustable) VFB_ADJ 0.985 1 1.015 V VIN = 3.5V, max operating VIN 8
Feedback voltage (5V) VFB_5V 4.925 5 5.075 V VIN = 5.5V, max operating VIN 8
Feedback voltage (3.3V) VFB_3p3V 3.25 3.3 3.35 V VIN = 3.8V, max operating VIN 8
FB input leakage current (adjustable) IFB_ADJ 0.2 100 nA FB = 1.0V 8
FB input leakage current (5V) IFB_5V 2.89 3.4 µA FB = 5.0V 8
FB input leakage current (3.3V) IFB_3p3V 1.67 2 µA FB = 3.3V 8
Hiccup threshold on FB pin VHICCUP 37 42 47 % 8
RESET upper threshold (rising FB voltage) VRESET-HIGH 110 112 115 % Rising FB voltage 9
RESET lower threshold (falling FB voltage) VRESET-LOW 91 93 95 % Falling FB voltage 9
RESET hysteresis VRESET-HYS 1.1 1.8 2.5 % FB voltage 9
Minimum input voltage for proper PG function VRESET_VALID 0.7 1.04 1.25 V VRESET less than 0.4V, 10kΩ pullup to external 5V 9
RESET on-resistance (VEN = 5.0V) RRESET 60 150 Ω VEN = 5.0V, 1mA pullup current 9
RESET on-resistance (VEN = 0V) RRESET 40 125 Ω VEN = 0V, 1mA pullup current 9

CAD (KiCad official)

  • Symbol: LM63635DQPWPRQ1
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: lm63635dqpwprq1-etched.step / lm63635dqpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm63635dqpwprq1.step / lm63635dqpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (59 pp, sha256 7d26ece346632163, retrieved 2026-10-27, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF