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LM5642MHX
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5642MHX
Texas Instruments · DC-DC Converters · HTSSOP-28-EP
LM5642MHX from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | KS1 | input | Positive Kelvin sense input for the Channel 1 current-sense amplifier, which must be routed on a separate trace and connected to VIN as close as possible to the current-sense resistor (or to the upper MOSFET drain when no sense resistor is used). |
| 2 | ILIM1 | passive | Channel 1 current-limit threshold pin that sinks a constant 9.9 µA through a resistor connected to VIN, and the resulting voltage is compared with the top MOSFET VDS or the sense-resistor voltage to detect overcurrent. |
| 3 | COMP1 | passive | Output of the internal transconductance error amplifier for Channel 1, with the loop compensation network connected between this pin and SGND (pin 8). |
| 4 | FB1 | input | Channel 1 feedback input, connected to VOUT through a voltage divider to set the output voltage adjustable from 1.3V to 90% of Vin. |
| 5 | SYNC | input | Switching-frequency synchronization input: LOW free-runs at 200 kHz (LM5642) or 375 kHz (LM5642X) with channels 180° out of phase, HIGH waits for an external clock, and a falling edge starts Channel 1 HDRV with Channel 2 HDRV 2.5 µs later, requiring a SYNC pulse width greater than 100 ns; LOW operation requires a 220 kΩ resistor to signal ground. |
| 6 | UV_DELAY | passive | A capacitor from this pin to ground sets the output under-voltage protection delay, charged from a 5 µA source, with the system latching off when the pin reaches 2.3V (typical); connecting this pin to ground disables output under-voltage protection. |
| 7 | VLIN5 | power_out | Output of the internal 5V LDO derived from VIN that biases the chip and powers the bootstrap gate-drive circuitry, and it must be bypassed to SGND with a minimum of 4.7 µF ceramic capacitor. |
| 8 | SGND | power_in | Signal-level ground connection, which should be connected to the ground rail of the system. |
| 9 | ON/SS1 | input | Channel 1 enable pin, internally pulled up to one diode drop above VLIN5 and open-collector type, where pulling it below 1.2V turns off Channel 1 and pulling both ON/SS1 and ON/SS2 below 1.2V shuts down the whole chip, with an optional capacitor providing soft-start. |
| 10 | ON/SS2 | input | Channel 2 enable pin with the same behavior as ON/SS1 (pin 9), pulled below 1.2V to turn off Channel 2, and it may be connected to ON/SS1 for simultaneous startup or parallel operation. |
| 11 | FB2 | input | Channel 2 feedback input, connected to VOUT through a voltage divider to set the Channel 2 output voltage. |
| 12 | COMP2 | passive | Output of the internal transconductance error amplifier for Channel 2, with the loop compensation network connected between this pin and SGND (pin 8). |
| 13 | ILIM2 | passive | Channel 2 current-limit threshold setting with the same function as ILIM1 (pin 2). |
| 14 | KS2 | input | Positive Kelvin sense input for the Channel 2 current-sense amplifier, with the same function as KS1 (pin 1). |
| 15 | RSNS2 | input | Negative Kelvin sense input for Channel 2, connected to the low side of the current-sense resistor between VIN and the top MOSFET drain, or to the top MOSFET source when its RDS(on) is used for sensing, with a separate Kelvin trace. |
| 16 | SW2 | passive | Switch-node connection for Channel 2 to the source of the top MOSFET, which serves as the negative supply rail for the top-side gate driver HDRV2. |
| 17 | HDRV2 | output | Floating top-side gate-drive output for Channel 2 that rides on the SW2 switching-node voltage. |
| 18 | CBOOT2 | passive | Bootstrap capacitor connection that provides the positive supply rail for the Channel 2 top-side gate drive, connected to VDD2 through a diode with the bootstrap capacitor low side tied to SW2. |
| 19 | VDD2 | power_in | Supply rail for the Channel 2 low-side gate drive, connected to VLIN5 through a 4.7Ω resistor, bypassed to power ground with a ceramic capacitor of at least 1 µF, and tied to VDD1 (pin 24). |
| 20 | LDRV2 | output | Low-side gate-drive output for Channel 2. |
| 21 | PGND | power_in | Power ground connection for both channels, which should be connected to the ground rail of the system. |
| 22 | VIN | power_in | Power input for the chip that must be connected to the positive input rail and to the same voltage rail as the top FET drain (or the current-sense resistor when used). |
| 23 | LDRV1 | output | Low-side gate-drive output for Channel 1. |
| 24 | VDD1 | power_in | Supply rail for the Channel 1 low-side gate drive, which must be tied to VDD2 (pin 19). |
| 25 | CBOOT1 | passive | Bootstrap capacitor connection that provides the positive supply rail for the Channel 1 top-side gate drive, with the same connection rules as CBOOT2 (pin 18). |
| 26 | HDRV1 | output | Top-side gate-drive output for Channel 1, floating on the SW1 switching-node voltage with the same behavior as HDRV2 (pin 17). |
| 27 | SW1 | passive | Switch-node connection for Channel 1 to the source of the top MOSFET, serving as the negative supply rail for the top-side gate driver HDRV1, with the same connection rules as SW2 (pin 16). |
| 28 | RSNS1 | input | Negative Kelvin sense input for the Channel 1 current-sense amplifier, with the same connection rules as RSNS2 (pin 15). |
| 29 | DAP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Power Management (PMIC) |
| Pins | 29 |
CAD (KiCad official)
- Symbol:
LM5642MHX - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files:
lm5642mhx-etched.step/lm5642mhx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5642mhx.step/lm5642mhx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
08d8cf8715d650c6, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).