component
LM5576MH
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5576MH
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
LM5576MH from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_out | Bias regulator output nominally regulated to 7.15V (range 6.85V to 7.45V) requiring 0.1µF to 1µF ceramic decoupling capacitor; external supply voltage 7.5V to 14V optional to reduce IC power dissipation. |
| 2 | SD | input | Shutdown/UVLO input enabling low-power mode for voltages >0.7V, standby mode 0.7V to 1.225V, and normal operation >1.225V, with internal 5µA pullup enabling full operation if pin left open. |
| 3 | VIN | power_in | Input power supply pin rated for 6V to 75V operation providing primary connection to internal voltage regulator and buck switch. |
| 4 | VIN | power_in | Input power supply pin rated for 6V to 75V operation providing secondary connection for power distribution. |
| 5 | SYNC | bidirectional | Oscillator synchronization input/output where external clock with open-drain output can pull low to synchronize internal oscillator, or multiple LM5576 devices synchronize by connecting SYNC pins together. |
| 6 | COMP | output | Error amplifier output for connection of type II compensation network (resistor-capacitor elements) between COMP and FB pins. |
| 7 | FB | input | Feedback input to error amplifier inverting input with 1.225V regulation threshold; output voltage set by external resistor divider as VOUT = 1.225V × (1 + R5/R6). |
| 8 | RT | input | Oscillator frequency programming input; external resistor connected between this pin and AGND sets internal oscillator frequency from 50kHz to 500kHz. |
| 9 | RAMP | output | Ramp control signal output; external capacitor to AGND (recommended 50pF to 2000pF) sets ramp slope for simulated current mode control. |
| 10 | AGND | power_in | Analog ground reference providing internal bias point for low-level signal circuits including oscillator, error amplifier, and synchronization functions. |
| 11 | SS | output | Soft start output pin with internal 10µA current source charging external capacitor to set error amplifier ramp time; held low during standby, VCC UVLO, and thermal shutdown. |
| 12 | OUT | power_out | Regulated output voltage connection directly to regulated output power with nominal voltage set by external resistor network as VOUT = 1.225V × (1 + R5/R6). |
| 13 | PGND | power_in | Power ground providing low-side return path for buck switch, gate driver circuits, and current sense resistor. |
| 14 | PGND | power_in | Power ground providing secondary connection for power return distribution and gate driver low-side reference. |
| 15 | IS | input | Current sense input connected to recirculation diode cathode; internal sense resistor detects diode current at end of off-time for simulated current ramp generation. |
| 16 | IS | input | Current sense input providing second connection for recirculation diode current measurement and direct current slope compensation feedback. |
| 17 | SW | output | Switch node output serving as source terminal of internal 75V, 170mΩ N-channel buck MOSFET connecting to external Schottky diode cathode and buck inductor. |
| 18 | SW | output | Switch node output providing second connection for internal N-channel buck switch source terminal; voltage switches between approximately -0.5V (off-time) and VIN (on-time). |
| 19 | PRE | input | Bootstrap capacitor pre-charge input with open-drain output connecting to SW pin to aid bootstrap capacitor charging at light load conditions; internal MOSFET conducts 265ns per cycle. |
| 20 | BST | input | Bootstrap input where external ceramic capacitor (0.022µF recommended) between BST and SW pins charges from VCC through internal diode during buck switch off-time for gate driver supply. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
LM5576MH - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP (KiCad packages3D, STEP)
- 3D model files:
lm5576mh-etched.step/lm5576mh-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5576mh.step/lm5576mh.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
6560aa111915f5a2, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).