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LM53602AQPWPRQ1

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Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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lm53602aqpwprq1-etched.glb lm53602aqpwprq1: factory component page (tier=lcsc) · Ray 15d ago
lm53602aqpwprq1-etched.step lm53602aqpwprq1: factory component page (tier=lcsc) · Ray 15d ago
lm53602aqpwprq1-hero.glb lm53602aqpwprq1: hero GLB from the etched model (keeps the MPN mark) · Ray 15d ago
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page.json lm53602aqpwprq1: specified limits as data (metadata.characteristics, 54 rows from the datasheet) · Ray 11d ago
README.md lm53602aqpwprq1: specified limits as data (metadata.characteristics, 54 rows from the datasheet) · Ray 11d ago

LM53602AQPWPRQ1

Texas Instruments · DC-DC Converters · HTSSOP-16-EP

LM53602AQPWPRQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW power_out Regulator switch node that connects to the power inductor; pins 1 and 2 must be connected directly together on the PCB.
2 SW power_out Regulator switch node that connects to the power inductor; pins 1 and 2 must be connected directly together on the PCB.
3 CBOOT power_in Bootstrap supply input for the gate drivers; connect a high-quality 470 nF capacitor from this pin to SW.
4 VCC power_out Internal 3.15 V regulator output supplying the internal control circuits; do not connect external loads, and connect a high-quality 3.3 µF capacitor from this pin to GND.
5 BIAS power_in Input to the internal voltage regulator that connects to the output voltage point and must not be grounded; connect a high-quality 0.1 µF capacitor from this pin to GND.
6 SYNC input Synchronization input that locks the regulator switching frequency to a system clock (FSYNC range 1.9 MHz to 2.3 MHz); connect to GND when not used and do not float.
7 FPWM input Mode control input where high selects forced PWM and low selects auto mode with automatic PFM/PWM transition; do not float.
8 RESET output Open-drain reset output that must be pulled up to a suitable supply through a current-limiting resistor, going high for power OK and low for fault or when EN is low; RESET pin current is limited to 1 mA in recommended operating conditions.
9 FB input Feedback input connected to the output sense point for the fixed 5 V and 3.3 V options or to the feedback divider tap for the ADJ option; do not float or ground.
10 AGND power_in Analog ground for the regulator and system to which all electrical parameters are measured; connect to EP and PGND on the PCB.
11 EN input Enable input where high turns the regulator on and low turns it off; it can be connected directly to VIN and must not float.
12 VIN power_in Input supply to the regulator with recommended input voltage of 3.9 V to 36 V; connect high-quality bypass capacitors from this pin to PGND and connect pins 12 and 13 directly together on the PCB.
13 VIN power_in Input supply to the regulator with recommended input voltage of 3.9 V to 36 V; connect high-quality bypass capacitors from this pin to PGND and connect pins 12 and 13 directly together on the PCB.
14 N/C unconnected No connection to the device.
15 PGND power_in Power ground for the internal low-side MOSFET that connects to AGND and system ground; pins 15, 16 must be connected directly together on the PCB.
16 PGND power_in Power ground for the internal low-side MOSFET that connects to AGND and system ground; pins 15, 16 must be connected directly together on the PCB.
17 EP power_in Exposed die attach paddle that must be connected to the ground plane for adequate heat sinking and noise reduction.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Power Supply Chip
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage 3.9 36 V 5
Output voltage: Fixed 5 V 0 5 V 5
Output voltage: Fixed 3.3 V 0 3.3 V 5
Output voltage adjustment range: ADJ 3.3 6 V 5
Output current for LM53602-Q1 0 2 A 5
RESET pin current 0 1 mA 5
Operating junction temperature -40 150 °C 5
VIN to AGND, PGND -0.3 40 V 4
SW to AGND, PGND -0.3 V max printed as VIN + 0.3 V 4
CBOOT to SW -0.3 3.6 V 4
EN to AGND, PGND -0.3 40 V 4
BIAS to AGND, PGND -0.3 16 V 4
FB to AGND, PGND -0.3 16 V fixed 5 V and 3.3 V 4
FB to AGND, PGND -0.3 5.5 V ADJ 4
RESET to AGND, PGND -0.3 8 V 4
SYNC, FPWM to AGND, PGND -0.3 5.5 V 4
VCC to AGND, PGND -0.3 4.2 V 4
RESET Pin Current -0.1 1.2 mA 4
AGND to PGND -0.3 0.3 V 4
Storage temperature Tstg -40 150 °C 4
Initial reference voltage accuracy -1 1 % VIN = 3.8 V to 36 V, FPWM, TJ = 25°C; FB for 5 V and 3.3 V options 6
Initial reference voltage accuracy -1.25 1.25 % VIN = 3.8 V to 36 V, FPWM 6
Reference voltage for ADJ option VREF 0.993 1 1.007 V VIN = 3.8 V to 36 V, FPWM, TJ = 25°C 6
Reference voltage for ADJ option VREF 0.99 1 1.01 V VIN = 3.8 V to 36 V, FPWM, TJ = -40°C to 125°C 6
Minimum input voltage to operate (rising) VIN-operate 3.2 3.95 V Rising 6
Minimum input voltage to operate (falling) VIN-operate 2.9 3.55 V Falling 6
Operating quiescent current IQ 8 13 µA VBIAS = 5 V, measured at VIN pin, TJ = -40°C to 125°C 6
Current into the BIAS pin IB 47 78 µA VBIAS = 5 V, FPWM = 3.3 V 6
RESET upper threshold voltage 105 107 110 % Rising, % of nominal Vout 6
RESET lower threshold voltage 92 94 96.5 % Falling, % of nominal Vout 6
Low level RESET pin output voltage VOL 0.4 V 50 µA pull-up to RESET pin, VIN = 1.5 V, EN = 0 V 6
Enable input threshold voltage VEN 1.7 2 V Rising 6
Enable input threshold voltage hysteresis VEN 0.45 0.55 V Hysteresis, below 6
Logic input high level on FPWM and SYNC pins VIH 1.5 V Logic input levels on FPWM and SYNC pins 6
Logic input low level on FPWM and SYNC pins VIL 0.4 V Logic input levels on FPWM and SYNC pins 6
High side switch current limit (LM53602-Q1) IHS 2.4 4.4 A 6
Low side switch current limit (LM53602-Q1) ILS 2 2.4 2.8 A 7
High side MOSFET resistance Rdson 135 290 mΩ 7
Low side MOSFET resistance Rdson 60 125 mΩ 7
Switching frequency FSW 1.85 2.1 2.35 MHz VIN = 3.8 V to 18 V 7
Synchronizing frequency range FSYNC 1.9 2.1 2.3 MHz 7
Thermal shutdown threshold TSD 162 178 °C Rising 7
Minimum switch on-time TON 50 80 ns VIN = 20 V 8
Minimum switch off-time TOFF 125 200 ns VIN = 3.8 V 8
Delay time to RESET high signal TRESET-act 2 3 4 ms 8
Glitch filter time for RESET function TRESET-filter 12 25 45 µs 8
Soft-start time TSS 1 2 3 ms 8
Turn-on delay TEN 0.7 0.8 ms CVCC = 1 µF 8
Junction-to-ambient thermal resistance RθJA 38.9 °C/W JESD 51-7, 4-layer JEDEC board 5
Junction-to-case (top) thermal resistance RθJC(top) 24.3 °C/W JESD 51-7, 4-layer JEDEC board 5
Junction-to-board thermal resistance RθJB 19.9 °C/W JESD 51-7, 4-layer JEDEC board 5
Junction-to-top characterization parameter ψJT 0.7 °C/W JESD 51-7, 4-layer JEDEC board 5
Junction-to-board characterization parameter ψJB 19.7 °C/W JESD 51-7, 4-layer JEDEC board 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 1.7 °C/W JESD 51-7, 4-layer JEDEC board 5

CAD (KiCad official)

  • Symbol: LM53602AQPWPRQ1
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: lm53602aqpwprq1-etched.step / lm53602aqpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm53602aqpwprq1.step / lm53602aqpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 b2d0d78814aaf2aa, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF