component

LM53602AMPWPT

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM53602AMPWPT

Texas Instruments · DC-DC Converters · HTSSOP-16-EP

LM53602AMPWPT from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW power_out Regulator switch node that connects to the power inductor, and pins 1 and 2 must be connected directly together at the PCB.
2 SW power_out Second regulator switch node pin, which must be connected directly to pin 1 at the PCB.
3 CBOOT power_in Bootstrap supply input for the gate drivers, connected through a high-quality 470-nF capacitor to SW, with CBOOT to SW rated at -0.3 V to 3.6 V.
4 VCC power_out Internal 3.15-V regulator output that supplies internal control circuits, must not be connected to any external loads, and needs a high-quality 3.3-µF capacitor to GND.
5 BIAS power_in Input to the internal voltage regulator that connects to the output voltage point, must not be grounded, and needs a high-quality 0.1-µF capacitor to GND.
6 SYNC input Synchronization input that locks the regulator switching frequency to the system clock within the 1.9 MHz to 2.3 MHz synchronizing range, and must be connected to GND when not used and not left floating.
7 FPWM input Mode control input where high selects forced PWM and low selects auto mode with automatic PFM/PWM transition, and it must not be left floating.
8 RESET output Open-drain reset output that goes high when power is OK and low on a fault or when EN is low, must be connected to a suitable supply through a current-limiting resistor, and has a pin current rating of -0.1 mA to 1.2 mA.
9 FB input Feedback input that connects to the output sense point for the fixed 5-V and 3.3-V options or to the feedback divider tap for the ADJ option, and must not be left floating or grounded.
10 AGND power_in Analog ground for the regulator and system against which all electrical parameters are measured, to be connected to EP and PGND on the PCB.
11 EN input Enable input where high turns the regulator on and low turns it off, which can be connected directly to VIN but must not be left floating.
12 VIN power_in Input supply to the regulator that requires a high-quality bypass capacitor to PGND, with pins 12 and 13 connected directly together at the PCB.
13 VIN power_in Second input supply pin that must be connected directly to pin 12 at the PCB.
14 N/C unconnected No connection; this pin has no connection to the device.
15 PGND power_in Power ground for the internal low-side MOSFET that connects to AGND and system ground, with pins 15 and 16 connected directly together at the PCB.
16 PGND power_in Second power ground pin that must be connected directly to pin 15 at the PCB.
17 EP power_in Exposed die attach paddle that must be connected to the ground plane for adequate heat sinking and noise reduction.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Power Supply Chip
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN to AGND, PGND VIN -0.3 40 V 4
SW to AGND, PGND SW -0.3 V 4
CBOOT to SW CBOOT -0.3 3.6 V 4
EN to AGND, PGND EN -0.3 40 V 4
BIAS to AGND, PGND BIAS -0.3 16 V 4
FB to AGND, PGND FB -0.3 5.5 V ADJ option 4
RESET to AGND, PGND RESET -0.3 8 V 4
SYNC, FPWM to AGND, PGND SYNC, FPWM -0.3 5.5 V 4
VCC to AGND, PGND VCC -0.3 4.2 V 4
RESET pin current -0.1 1.2 mA 4
AGND to PGND -0.3 0.3 V 4
Storage temperature Tstg -40 150 °C 4
Input voltage 3.9 36 V 5
Output voltage adjustment range: ADJ 3.3 10 V ADJ option 5
Output current for LM53602 0 2 A 5
RESET pin current 0 1 mA 5
Operating junction temperature TJ -40 150 °C 5
Reference voltage for ADJ option VREF 0.993 1 1.007 V VIN = 3.8 V to 36 V, FPWM, TJ = 25°C 6
Reference voltage for ADJ option VREF 0.99 1 1.01 V VIN = 3.8 V to 36 V, FPWM, TJ = –40°C to 125°C 6
Minimum input voltage to operate, rising VIN-operate 3.2 3.95 V Rising 6
Minimum input voltage to operate, falling VIN-operate 2.9 3.55 V Falling 6
Operating quiescent current IQ 8 13 µA VBIAS = 5 V, TJ = –40°C to 125°C; measured at VIN pin 6
Current into the BIAS pin IB 47 78 µA VBIAS = 5 V, FPWM = 3.3 V 6
RESET upper threshold voltage VRESET 105 107 110 % Rising, % of nominal Vout 6
RESET lower threshold voltage VRESET 92 94 96.5 % Falling, % of nominal Vout 6
RESET lower threshold voltage with respect to output voltage VRESET 94.5 95.7 % Falling, % actual Vout 6
Logic input high level on FPWM and SYNC pins VIH 1.5 V Logic input levels on FPWM and SYNC pins 6
Logic input low level on FPWM and SYNC pins VIL 0.4 V Logic input levels on FPWM and SYNC pins 6
High-side switch current limit, LM53602 IHS 2.4 4.4 A LM53602 6
Low-side switch current limit, LM53602 ILS 2 2.4 2.8 A LM53602, valley current limit 6
Power switch on-resistance, high-side MOSFET Rdson 135 290 mΩ High-side MOSFET resistance 7
Power switch on-resistance, low-side MOSFET Rdson 60 125 mΩ Low-side MOSFET resistance 7
Switching frequency FSW 1.85 2.1 2.35 MHz VIN = 3.8 V to 18 V 7
Synchronizing frequency range FSYNC 1.9 2.1 2.3 MHz 7
Thermal shutdown threshold TSD 162 178 °C Rising 7
Enable input threshold voltage VEN 1.7 2 V Rising 6
Enable input threshold hysteresis VEN 0.45 0.55 V Hysteresis, below 6
Enable input threshold for full shutdown VEN-off 0.8 V EN input voltage required for complete shutdown of the regulator, falling 6
Low level RESET pin output voltage VOL 0.4 V 50-µA pullup to RESET pin, Vin = 1.5 V, EN = 0 V 6
Turnon time from switch on-time, minimum TON 50 80 ns Minimum switch on-time, VIN = 20 V 8
Minimum switch off-time TOFF 125 200 ns Minimum switch off-time, VIN = 3.8 V 8
Delay time to RESET high signal TRESET-act 2 3 4 ms 8
Glitch filter time for RESET function TRESET-filter 12 25 45 µs 8
Soft-start time TSS 1 2 3 ms 8
Shutdown quiescent current, 25°C ISD 1.7 µA EN ≤ 0.4 V, TJ = 25°C; measured at VIN pin 6
Shutdown quiescent current, 125°C ISD 3.5 µA EN ≤ 0.4 V, TJ = 125°C; measured at VIN pin 6
Current into EN pin IEN 2.3 µA VIN = VEN = 13.5 V 6
Bias current into FB pin IFB 10 nA ADJ option 6
RESET hysteresis as a percent of output voltage set point VRESET-Hyst 1.5 % 6
Minimum input voltage for proper RESET function VMIN 1.5 V 50-µA pullup to RESET pin, VEN = 0 V, TJ = 25°C 6
Zero-cross current limit IZC -0.02 A FPWM = 0 V 7
Negative current limit INEG -1.5 A FPWM = 3.3 V 7
Switching frequency at VIN = 36 V FSW 1.2 MHz VIN = 36 V 7
Internal VCC voltage VCC 3.15 V VBIAS = 3.3 V 7
Thermal shutdown hysteresis TSD 18 °C Hysteresis, below 7
Minimum input voltage to operate, hysteresis VIN-operate 0.34 V Hysteresis, below 6
Short-circuit wait time (hiccup time) TW 5.5 ms 8
Junction-to-ambient thermal resistance RθJA 42.5 °C/W PWP (HTSSOP) 16 pins 5

CAD (KiCad official)

  • Symbol: LM53602AMPWPT
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: lm53602ampwpt-etched.step / lm53602ampwpt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm53602ampwpt.step / lm53602ampwpt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 590d70f52aa0f37f, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF