component
LM53600AQDSXRQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, WSON-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownLM53600AQDSXRQ1
Texas Instruments · DC-DC Converters · WSON-10-EP(3x3)
LM53600AQDSXRQ1 from Texas Instruments, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | power_out | Regulator switch node; connect to the output inductor. |
| 2 | BOOT | input | High-side gate driver upper supply rail; connect a 100-nF capacitor from SW to BOOT, which an internal diode charges while the SW node is low. |
| 3 | VCC | power_out | Internal 3-V regulator output supplying the internal control circuits; connect a high-quality 1.0-µF capacitor from this pin to GND for the adjustable version. |
| 4 | FB | input | Adjustable version feedback input for output voltage only; connect to the output through a voltage divider that sets the output set point, with an adjustment range of 3.3 V to 6 V. |
| 5 | BIAS | power_in | Power source for the VCC regulator; connect to the output node with a 10-nF bypass capacitor placed immediately adjacent to this pin. |
| 6 | RESET | output | Open-drain reset output; connect to a suitable supply through a current-limiting pull-up resistor (high = regulator OK, low = regulator fault), and it goes low when EN is low; RESET sink current is limited to 8 mA. |
| 7 | EN | input | Enable input to the regulator (high = on, low = off); it can be connected to VIN and must not float. |
| 8 | VIN | power_in | Input supply to the regulator, with a recommended range of 3.8 V to 36 V after startup; connect input bypass capacitors directly between this pin and GND. |
| 9 | SYNC/MODE | input | Multifunction mode control input tolerant of voltages up to VIN: an external sync signal forces PWM synchronized to its rising edge, tied high forces PWM at the internal clock, tied low selects AUTO mode with diode emulation at light load, and it must not float. |
| 10 | GND | power_in | Ground pin; bypass to VIN with a capacitor placed immediately adjacent to this pin. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(3x3) |
| Category | Power Supply Chip |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND | VIN | -0.3 | 42 | V | Footnote 1: 42 V for ≤100 ms at duty cycle ≤1% | 5 | |
| SW to GND | SW | -0.3 | V | 5 | |||
| BOOT to SW | BOOT | -0.3 | 3.6 | V | 5 | ||
| EN to GND | EN | -0.3 | 42 | V | Footnote 1: 42 V for ≤100 ms at duty cycle ≤1% | 5 | |
| BIAS to GND (LM53600-Q1-ADJ) | BIAS | -0.3 | 16 | V | 5 | ||
| FB to GND (LM53600-Q1-ADJ) | FB | -0.3 | 5.5 | V | 5 | ||
| RESET to GND | RESET | -0.3 | 8 | V | 5 | ||
| RESET sink current | 8 | mA | 5 | ||||
| SYNC/MODE to GND | SYNC/MODE | -0.3 | 42 | V | Footnote 1: 42 V for ≤100 ms at duty cycle ≤1% | 5 | |
| VCC | VCC | -0.3 | 3.6 | V | 5 | ||
| Storage temperature | Tstg | -40 | 150 | °C | 5 | ||
| Input voltage range after startup | 3.8 | 36 | V | After startup | 5 | ||
| Output adjustment range (LM53600-Q1-ADJ) | 3.3 | 6 | V | LM53600-Q1-ADJ | 5 | ||
| Load current range (LM53600-Q1) | 0 | 650 | mA | LM53600-Q1 | 5 | ||
| Operating junction temperature | -40 | 150 | °C | 5 | |||
| Initial output voltage accuracy | VFB | -1 | 1 | % | Vin = 3.8 V to 36 V, Tj = 25°C, Open Loop | 6 | |
| Initial output voltage accuracy | VFB | -1.5 | 1.5 | % | Vin = 3.8 V to 36 V, Open Loop | 6 | |
| Minimum input voltage to operate (UVLO rising) | Vin_UVLO | 3.2 | 3.6 | 3.75 | V | Rising | 6 |
| Minimum input voltage hysteresis | Vin_UVLO_hyst | 0.2 | 0.3 | 0.35 | V | Hysteresis | 6 |
| RESET upper threshold voltage | Vreset_OV | 105 | 106.5 | 110 | % | Rising, % of Vout | 6 |
| RESET lower threshold voltage | Vreset_UV | 92 | 94 | 97 | % | Falling, % Vout | 6 |
| Switching frequency (without spread spectrum) | Fsw | 1.89 | 2.1 | 2.4 | MHz | VIN = 13.5 V, Without spread spectrum, PWM operation | 7 |
| Sync frequency range | FSYNC | 1.9 | 2.1 | 2.3 | MHz | Output setting + 1 V < VIN < 18 V | 7 |
| Sync input duty cycle range | DSYNC | 25 | 75 | % | High state input < 5.5 V and > 2.3 V | 7 | |
| High side switch current limit | IL_HS | 1 | 1.35 | 1.65 | A | LM53600-Q1; duty cycle approaches 0% | 7 |
| Low side switch current limit | IL_LS | 0.65 | 0.78 | 0.93 | A | LM53600-Q1 | 7 |
| Enable input threshold voltage - rising | VEN | 1.7 | 2 | V | Enable rising | 7 | |
| Enable threshold hysteresis | VEN_HYST | 0.4 | 0.55 | V | 7 | ||
| Output voltage ADJ option (FPWM) | Vout_ADJ | -2 | 2 | % | VIN = VOUT + 0.6 V to 36 V, IOUT = 100 mA, FPWM mode | 8 | |
| Output voltage ADJ option (Auto mode) | Vout_ADJ | -2 | 2.5 | % | VIN = VOUT + 0.6 V to 36 V, IOUT = 100 µA to 100 mA, Auto mode | 8 | |
| Reference voltage for ADJ option | Vref | 0.993 | 1 | 1.007 | V | Tj = 25°C | 8 |
| Reference voltage for ADJ option | Vref | 0.985 | 1 | 1.015 | V | 8 | |
| Thermal shutdown rising threshold | TSD | 151 | 167 | 185 | °C | 8 | |
| Soft-start time | tSS | 1.3 | 3 | 4.5 | ms | Time from first SW node pulse to Vref at 90%, VIN ≥ 4.2 V | 9 |
| Delay time to RESET high signal | treset_act | 4 | 6 | 8 | ms | 9 | |
| Junction-to-ambient thermal resistance | Rθ JA | 46.2 | °C/W | DSX (WSON) 10-pin | 6 | ||
| Junction-to-case (top) thermal resistance | Rθ JC | 31.5 | °C/W | DSX (WSON) 10-pin | 6 | ||
| Junction-to-board thermal resistance | Rθ JB | 20.9 | °C/W | DSX (WSON) 10-pin | 6 | ||
| Junction-to-top characterization parameter | φJT | 0.3 | °C/W | DSX (WSON) 10-pin | 6 | ||
| Junction-to-board characterization parameter | φJB | 21 | °C/W | DSX (WSON) 10-pin | 6 | ||
| Junction-to-case (bottom) thermal resistance | Rθ JC(bot) | 4.1 | °C/W | DSX (WSON) 10-pin | 6 |
CAD (KiCad official)
- Symbol:
LM53600AQDSXRQ1 - Footprint:
Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm - 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
lm53600aqdsxrq1-etched.step/lm53600aqdsxrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm53600aqdsxrq1.step/lm53600aqdsxrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
d174c97c59a34282, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).