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LM5185QPWPRQ1

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Texas Instruments DC-DC Converters, HTSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM5185QPWPRQ1

Texas Instruments · DC-DC Converters · HTSSOP-14

LM5185QPWPRQ1 from Texas Instruments, in a HTSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable and UVLO programming pin: below 1.1 V the converter is in shutdown, between 1.1 V and 1.5 V it is in standby, and above 1.5 V the start-up sequence begins.
2 NC unconnected No electrical connection.
3 TC input Temperature compensation pin; a resistor between TC and RSET compensates the temperature coefficient of the secondary diode forward voltage (TC voltage 1 V typical at ITC = ±10 µA).
4 RSET input Reference-current pin for FB; a 10 kΩ resistor from RSET to GND sets the regulated RSET voltage of 1 V typical.
5 AGND power_in Analog ground, the ground connection for the internal control circuitry.
6 SS input Soft-start input; a capacitor from SS to AGND sets the start-up time and input inrush current, and if SS is left open an internal 6 ms soft-start timer is used.
7 COMP output Transconductance error amplifier output; the compensation network is connected between COMP and AGND.
8 PGND power_in Power ground, the ground connection for the gate driver.
9 CS input Current-sense input, connected by a short path to the positive side of the current-sense resistor; the peak current-limit threshold is 100 mV maximum at the sense input.
10 VCC power_out Output of the internal VCC regulator and supply input for the MOSFET driver; place a ceramic bypass capacitor between VCC and PGND, with a recommended range of 1 µF to 4.7 µF, and VCC regulates to 7 V typical with an absolute maximum of 15 V.
11 GATE output N-channel MOSFET gate drive output, connected through a short low-inductance path directly to the MOSFET gate; absolute maximum is VVCC + 0.3 V.
12 NC unconnected No electrical connection.
13 FB input Primary-side feedback pin; a resistor between FB and SW together with the RSET resistor sets the output voltage, and the pin is rated to 105 V to AGND.
14 VIN power_in Input supply connection that powers the internal bias regulator and the input-voltage sense; the recommended operating input range is 4.5 V to 100 V.
15 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-14
Category Power Management (PMIC)
Pins 15

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN to AGND -0.3 105 V TJ -40 to 150°C unless noted 4
EN/UVLO to AGND -0.3 105 V TJ -40 to 150°C unless noted 4
TC to AGND -0.3 5.5 V TJ -40 to 150°C unless noted 4
SS to AGND -0.3 5.5 V TJ -40 to 150°C unless noted 4
FB to AGND -0.3 105 V TJ -40 to 150°C unless noted 4
FB to VIN -0.3 0.3 V TJ -40 to 150°C unless noted 4
RSET to AGND -0.3 3 V TJ -40 to 150°C unless noted 4
CS to AGND -0.3 0.3 V TJ -40 to 150°C unless noted 4
VCC to AGND -0.3 15 V TJ -40 to 150°C unless noted 4
PGND to AGND -0.3 0.3 V TJ -40 to 150°C unless noted 4
GATE to AGND (max VVCC + 0.3) -0.3 V TJ -40 to 150°C unless noted 4
GATE to AGND (20 ns transient) -1.5 V 20 ns transient 4
COMP to AGND -0.3 5.5 V TJ -40 to 150°C unless noted 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -55 150 °C 4
Input voltage after turn-on VVIN 4.5 100 V 4
EN/UVLO voltage VEN/UVLO 100 V 4
FB voltage VFB 100 V 4
VCC voltage VVCC 4.5 14 V 4
Operating junction temperature (recommended) TJ -40 150 °C 4
VIN active current IACTIVE 425 575 µA VEN/UVLO = 2.5V, VRSET = 1.8V 5
VIN active current with external VCC IACTIVE-VCC 25 40 µA VVCC = 8V 5
Enable threshold, EN/UVLO rising VUV-RISING 1.45 1.5 1.53 V 5
Enable voltage hysteresis VUV-HYST 0.04 0.05 V VEN/UVLO falling 5
Enable current hysteresis IUV-HYST 4.75 5 5.25 µA VEN/UVLO = 1.6V 5
RSET regulation voltage VRSET 0.99 1 1.01 V RRSET = 10kΩ 5
FB to VIN voltage (1) VFB-VIN1 -40 mV IFB = 80µA 5
FB to VIN voltage (2) VFB-VIN2 40 mV IFB = 120µA 5
Standby threshold, EN/UVLO rising VSD-RISING 0.8 1.1 V VEN/UVLO rising 5
Peak current limit threshold (max) VCS-MAX 95 100 105 mV 5
Peak current limit threshold (min) VCS-MIN 18 20 22 mV 5
TC voltage VTC 1 1.05 V ITC = ±10µA, TJ = 25°C 6
GATE output low voltage VGATE-LOW 0.02 V 6
GATE output high voltage VGATE-HIGH 0.07 V 6
Minimum switching frequency FSW-MIN 11 kHz 5
Maximum switching frequency FSW-MAX 350 kHz 5
Minimum switch on-time tON-MIN 125 ns 5
VIN shutdown current ISHUTDOWN 1.7 µA VEN/UVLO = 0V 5
VCC regulation voltage VVCC-REG 7 V 5
VCC UVLO rising threshold VVCC-UVLO 4.25 V 5
VCC UVLO hysteresis VVCC-HYST 0.35 V 5
VCC sourcing current limit IVCC-LIM 30 mA 5
Shutdown threshold, EN/UVLO falling VSD-FALLING 0.3 V VEN/UVLO falling 5
RSET current IRSET 100 µA RRSET = 10kΩ 5
EA transconductance gm 600 uS 5
COMP source current ICOMP-SRC 100 µA 5
COMP sink current ICOMP-SNK -100 µA 5
GATE output rise time tGATE-RISE 30 ns 6
GATE output fall time tGATE-FALL 15 ns 6
SS external capacitor charge current ISS 5 µA 6
Internal SS time tSS 6 ms 6
Peak current limit response time tCS-DELAY 35 ns 6
Thermal shutdown threshold (TJ rising) TSD 175 °C 6
Thermal shutdown hysteresis TSD-HYS 10 °C 6
Junction-to-ambient thermal resistance RΘJA 52.8 °C/W 5
Junction-to-case (top) thermal resistance RΘJC(top) 49.3 °C/W 5
Junction-to-board thermal resistance RΘJB 28.3 °C/W 5
Junction-to-top characterization parameter ΨJT 2.8 °C/W 5
Junction-to-board characterization parameter ΨJB 28.1 °C/W 5
Junction-to-case (bottom) thermal resistance RΘJC(bot) 11.2 °C/W 5

CAD (KiCad official)

  • Symbol: LM5185QPWPRQ1
  • Footprint: Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: lm5185qpwprq1-etched.step / lm5185qpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5185qpwprq1.step / lm5185qpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 4c73add249ee4964, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF