component
LM5176RHFT
Public Made by Adomby adom
Texas Instruments DC-DC Converters, QFN-28-EP(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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LM5176RHFT
Texas Instruments · DC-DC Converters · QFN-28-EP(4x5)
LM5176RHFT from Texas Instruments, in a QFN-28-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MODE | input | Hiccup-mode select pin: 1.38 V < MODE < 2.22 V enables hiccup, and 2.6 V < MODE < VCC disables it, set by RMODE to AGND (93.1 kΩ or 200 kΩ). |
| 2 | DITH | input | Dither capacitor pin that modulates the oscillator frequency by 10% of the RT-set nominal frequency; grounding it disables dithering. |
| 3 | RT/SYNC | input | Switching frequency programming pin set by a resistor to AGND, which can also accept an external sync clock; the operating frequency range is 100 kHz to 600 kHz. |
| 4 | SLOPE | input | A capacitor from SLOPE to AGND provides the slope compensation ramp for stable current-mode operation in buck and boost modes. |
| 5 | SS | input | Soft-start programming pin; a capacitor from SS to AGND sets the soft-start time. |
| 6 | COMP | output | Error amplifier output, with an external RC network to AGND for loop compensation; the COMP range is 0.3 V to 3 V. |
| 7 | AGND | power_in | Analog ground of the IC, to which the PowerPAD is soldered. |
| 8 | FB | input | Feedback input for output voltage regulation, connected through a resistor divider from VOUT; PGOOD trips outside -9%/+10% of the 0.8 V VREF. |
| 9 | VOSNS | input | Output voltage sense input, connected to the power stage output rail; the VOUT range is 0.8 V to 55 V. |
| 10 | ISNS(-) | input | Negative input of the current sense amplifier; the common mode range is 0 V to 55 V and a 50 mV sensed drop activates constant-current control. |
| 11 | ISNS(+) | input | Positive input of the current sense amplifier; shorting ISNS(+) to ISNS(-) disables the average current limit. |
| 12 | CSG | input | Negative (ground) input of the PWM current sense amplifier, connected directly to the low side of the current sense resistor; CS and CSG are limited to ±0.3 V. |
| 13 | CS | input | Positive input of the PWM current sense amplifier, referenced to CSG with a ±0.3 V limit. |
| 14 | PGOOD | output | Open-drain power-good output, pulled low when FB is outside the -9%/+10% window; it can be pulled up to 8 V. |
| 15 | SW2 | input | Boost-side switching node; the absolute maximum is 60 V (-1 V to 60 V). |
| 16 | HDRV2 | output | High-side gate driver output for the boost-side MOSFET, sourcing 1.8 A and sinking 2.2 A peak. |
| 17 | BOOT2 | power_out | Bootstrap pin for the boost-side high-side driver; an external capacitor from BOOT2 to SW2 is required, typically 0.1 µF to 0.22 µF at 16 V or higher. |
| 18 | LDRV2 | output | Low-side gate driver output for the boost-side MOSFET, sourcing 1.8 A and sinking 2.2 A peak. |
| 19 | PGND | power_in | Power ground of the IC and the high-current return for the low-side gate drivers. |
| 20 | VCC | power_out | Output of the VCC bias regulator, which requires a capacitor to ground; VCC is limited to 8.5 V absolute maximum. |
| 21 | BIAS | power_in | Optional bias input to the VCC regulator to reduce power loss at high VIN; the BIAS range is 8 V to 36 V when VCC is in regulation. |
| 22 | LDRV1 | output | Low-side gate driver output for the buck-side MOSFET, sourcing 1.8 A and sinking 2.2 A peak. |
| 23 | BOOT1 | power_out | Bootstrap pin for the buck-side high-side driver; an external capacitor from BOOT1 to SW1 is required, typically 0.1 µF to 0.22 µF at 16 V or higher. |
| 24 | HDRV1 | output | High-side gate driver output for the buck-side MOSFET, sourcing 1.8 A and sinking 2.2 A peak. |
| 25 | SW1 | input | Buck-side switching node; the absolute maximum is 60 V (-1 V to 60 V). |
| 26 | EN/UVLO | input | Enable pin: EN/UVLO below 0.4 V gives shutdown, and above 1.22 V enables switching once VCC exceeds its UV threshold; the range is 0 V to 55 V. |
| 27 | VIN | power_in | Input supply pin, connected to a supply between 4.2 V and 55 V (60 V absolute maximum). |
| 28 | VISNS | input | Input voltage sense pin, connected to the power stage input rail; with external bias the range is 2.5 V to 55 V. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-28-EP(4x5) |
| Category | Power Management (PMIC) |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input bias voltage | VIN | 4.2 | 55 | V | 5 | ||
| Input power stage voltage with external bias | VISNS | 2.5 | 55 | V | BIAS ≥ 5 V or VIN ≥ 4.5 V | 5 | |
| Bias supply voltage (when VCC in regulation) | BIAS | 8 | 36 | V | when VCC in regulation | 5 | |
| Output voltage range | VOSNS | 0.8 | 55 | V | 5 | ||
| Enable voltage range | EN/UVLO | 0 | 55 | V | 5 | ||
| Average current sense common mode range | ISNS(+), ISNS(-) | 0 | 55 | V | 5 | ||
| Operating temperature | TJ | -40 | 125 | °C | 5 | ||
| Operating frequency | fsw | 100 | 600 | kHz | 5 | ||
| Input voltage absolute maximum | VIN, EN/UVLO, VISNS, VOSNS, ISNS(+), ISNS(-) | -0.3 | 60 | V | 5 | ||
| Bias absolute maximum | BIAS | -0.3 | 40 | V | 5 | ||
| Low-voltage pin absolute maximum | FB, SS, DITH, RT/SYNC, SLOPE, COMP | -0.3 | 3.6 | V | 5 | ||
| Switch node absolute maximum | SW1, SW2 | -1 | 60 | V | 5 | ||
| Switch node absolute maximum transient | SW1, SW2 | -5 | 65 | V | 20 ns transient | 5 | |
| VCC, MODE, PGOOD absolute maximum | VCC, MODE, PGOOD | -0.3 | 8.5 | V | 5 | ||
| Low-side driver absolute maximum | LDRV1, LDRV2 | -0.3 | 8.5 | V | 5 | ||
| High-side driver absolute maximum, BOOT1 and HDRV1 with respect to SW1 | BOOT1, HDRV1 | -0.3 | 8.5 | V | with respect to SW1 | 5 | |
| High-side driver absolute maximum, BOOT2 and HDRV2 with respect to SW2 | BOOT2, HDRV2 | -0.3 | 8.5 | V | with respect to SW2 | 5 | |
| Bootstrap absolute maximum | BOOT1, BOOT2 | -0.3 | 68 | V | 5 | ||
| Current sense differential absolute maximum | ISNS(+) with respect to ISNS(-) | -0.3 | 0.3 | V | 5 | ||
| PWM current sense absolute maximum | CS, CSG | -0.3 | 0.3 | V | 5 | ||
| Operating junction temperature absolute maximum | -40 | 150 | °C | 5 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| VCC regulation voltage | VVCC(VIN) | 6.95 | 7.35 | 7.88 | V | VBIAS = 0 V, VCC open | 6 |
| VCC undervoltage lockout | VUV(VCC) | 3.11 | 3.27 | 3.43 | V | VCC increasing | 6 |
| VIN shutdown current | IQ | 2.6 | 10 | µA | VEN/UVLO = 0 V | 6 | |
| VIN operating current | 2 | 4 | mA | VEN/UVLO = 2 V, VFB = 0.9 V | 6 | ||
| BIAS switchover voltage | VBIAS(SW) | 7.25 | 8 | 8.75 | V | VIN = 24 V | 6 |
| Standby threshold | VEN(STBY) | 0.55 | 0.82 | 0.97 | V | EN/UVLO rising | 6 |
| Standby source current | IEN(STBY) | 1 | 2 | 3 | µA | VEN/UVLO = 1.1 V | 6 |
| Operating threshold | VEN(OP) | 1.17 | 1.22 | 1.29 | V | EN/UVLO rising | 6 |
| Operating hysteresis current | ΔIHYS(OP) | 2.15 | 3.15 | 4.25 | µA | VEN/UVLO = 1.5 V | 6 |
| Soft-start pullup current | ISS | 3.75 | 5 | 6.35 | µA | VSS = 0 V | 6 |
| Feedback reference voltage | VREF | 0.788 | 0.8 | 0.812 | V | FB = COMP | 6 |
| Switching frequency 1 | fSW(1) | 175 | 200 | 225 | kHz | RT = 40 kΩ | 6 |
| Switching frequency 2 | fSW(2) | 350 | 390 | 430 | kHz | RT = 20 kΩ | 6 |
| Buck current limit threshold (Valley, QFN-28) | VCS(BUCK) | 60 | 80 | 94 | mV | VIN = VVISNS = 24 V, VVOSNS = 12 V, VSLOPE = 0 V | 7 |
| Boost current limit threshold (Peak, QFN-28) | VCS(BOOST) | 96 | 120 | 140 | mV | VIN = VVISNS = 12 V, VVOSNS = 18 V, VSLOPE = 0 V | 7 |
| Average current loop regulation target | VSNS | 43 | 50 | 57 | mV | VISNS(-) = 24 V, sweep ISNS(+), VSS = 0.8 V | 7 |
| Buck adaptive slope current | ISLOPE | 24 | 30 | 35 | µA | VIN = VVISNS = 24 V, VVOSNS = 12 V, VSLOPE = 0 V | 7 |
| Boost adaptive slope current | ISLOPE | 13 | 17 | 21 | µA | VIN = VVISNS = 12 V, VVOSNS = 18 V, VSLOPE = 0 V | 7 |
| Source current out of MODE pin | IMODE | 17 | 20 | 23 | µA | 7 | |
| CCM with hiccup threshold | VCCM_HIC | 1.18 | 1.28 | 1.38 | V | 7 | |
| CCM no hiccup threshold | VCCM | 2.22 | 2.4 | 2.6 | V | 7 | |
| PGOOD sink current | ISINK(PGD) | 2 | 4.2 | 6.5 | mA | VPGOOD = 0.4 V | 8 |
| Thermal resistance junction-to-ambient (RHF QFN) | RθJA | 34.7 | °C/W | 6 | |||
| Thermal resistance junction-to-case (top) (RHF QFN) | RθJC(top) | 26.6 | °C/W | 6 | |||
| Thermal resistance junction-to-board (RHF QFN) | RθJB | 6.3 | °C/W | 6 | |||
| Junction-to-top characterization parameter (RHF QFN) | ψJT | 0.3 | °C/W | 6 | |||
| Junction-to-board characterization parameter (RHF QFN) | ψJB | 6.2 | °C/W | 6 | |||
| Junction-to-case (bottom) thermal resistance (RHF QFN) | RθJC(bot) | 2 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
LM5176RHFT - Footprint:
Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm - 3D model: QFN-28-EP(4x5) (KiCad packages3D, STEP)
- 3D model files:
lm5176rhft-etched.step/lm5176rhft-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5176rhft.step/lm5176rhft.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (45 pp, sha256
98191bec36d43771, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).