component
LM5175QPWPRQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5175QPWPRQ1
Texas Instruments · DC-DC Converters · HTSSOP-28
LM5175QPWPRQ1 from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN/UVLO | input | Enable pin with programmable UVLO threshold; shutdown <0.4V, standby 0.7-1.23V, operating >1.23V (requires VCC >3.3V). |
| 2 | VIN | power_in | Input supply pin; connect to supply voltage 3.5-42V nominal, 60V absolute maximum. |
| 3 | VISNS | input | Input voltage sense input; connect to input capacitor for VIN monitoring. |
| 4 | MODE | input | Mode selection input; sets CCM/DCM operation and enables/disables hiccup via RMODE resistor to GND (0Ω/49.9kΩ/93.1kΩ) or VCC. |
| 5 | DITH | input | Frequency dithering control pin; capacitor to AGND modulates frequency ±5% at 10µA charge/discharge, ground to disable. |
| 6 | RT/SYNC | input | Frequency programming input; external resistor to AGND sets switching frequency 100-600kHz, or external sync pulse 75-500ns at >2.1V threshold. |
| 7 | SLOPE | input | Slope compensation node; external capacitor to AGND provides adaptive ramp for stable current-mode control in buck and boost. |
| 8 | SS | input | Soft-start capacitor connection pin; capacitor to AGND programs startup time with 5µA pull-up current, clamped to 1.27V. |
| 9 | COMP | output | Error amplifier output for external compensation network; 0.3-3V output range, 1.27MΩ output impedance. |
| 10 | AGND | power_in | Analog ground reference for all analog signal paths and feedback circuits. |
| 11 | FB | input | Feedback input for output voltage regulation; referenced to 0.8V internal VREF, with ±10% PGOOD window. |
| 12 | VOSNS | input | Output voltage sense input; connect to output capacitor for VOUT monitoring. |
| 13 | ISNS(-) | input | Current sense amplifier negative input; forms 50mV regulation threshold with ISNS(+) for average current limiting. |
| 14 | ISNS(+) | input | Current sense amplifier positive input; forms 50mV regulation threshold with ISNS(-) for average input/output current limiting. |
| 15 | CSG | input | Ground reference for PWM current sense amplifier; connect directly to low-side of current sense resistor. |
| 16 | CS | input | Positive input to PWM current sense amplifier; connect to high-side of sense resistor; 76mV (buck) / 160mV (boost) cycle-by-cycle current limits. |
| 17 | PGOOD | output | Open-drain power good output; pulled low when FB voltage outside ±10% window around 0.8V reference (-9%/+10% hysteresis). |
| 18 | SW2 | output | Boost-side switching node; high-voltage switching output (−1 to 60V, 65V transient) for power stage and BOOT2 bootstrap circuit. |
| 19 | HDRV2 | output | High-side gate driver output for boost stage; sources 1.8A peak, sinks 2.2A peak with 55ns dead-time from LDRV2. |
| 20 | BOOT2 | passive | Bootstrap capacitor connection point; external capacitor between BOOT2 and SW2 provides 5.62V typical bias to HDRV2 gate driver. |
| 21 | LDRV2 | output | Low-side gate driver output for boost stage; sources 1.8A peak, sinks 2.2A peak with 55ns dead-time to HDRV2. |
| 22 | PGND | power_in | Power ground reference; high-current ground return for low-side gate drivers and power stage. |
| 23 | VCC | power_out | Regulated 7.5V output from internal bias regulator (6.95-7.88V); bypass with 1µF capacitor to PGND. |
| 24 | BIAS | power_in | Optional external bias supply input 8-36V; powers VCC regulator when VBIAS >8V to reduce power loss, must not exceed 40V. |
| 25 | LDRV1 | output | Low-side gate driver output for buck stage; sources 1.8A peak, sinks 2.2A peak with 55ns dead-time from HDRV1. |
| 26 | BOOT1 | passive | Bootstrap capacitor connection point; external capacitor between BOOT1 and SW1 provides 5.62V typical bias to HDRV1 gate driver. |
| 27 | HDRV1 | output | High-side gate driver output for buck stage; sources 1.8A peak, sinks 2.2A peak with 55ns dead-time to LDRV1. |
| 28 | SW1 | output | Buck-side switching node; high-voltage switching output (−1 to 60V, 65V transient) for power stage and BOOT1 bootstrap circuit. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28 |
| Category | Power Management (PMIC) |
| Pins | 29 |
CAD (KiCad official)
- Symbol:
LM5175QPWPRQ1 - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files:
lm5175qpwprq1-etched.step/lm5175qpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5175qpwprq1.step/lm5175qpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
02b7ec17407f0576, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).