component
LM5169PDDAR
Public Made by Adomby adom
TEXAS INSTRUMENTS Global Sourcing Parts, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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LM5169PDDAR
TEXAS INSTRUMENTS · Global Sourcing Parts · SOP-8-EP
LM5169PDDAR from TEXAS INSTRUMENTS, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground connection for internal circuits. |
| 2 | VIN | power_in | Regulator supply input to the high-side power MOSFET and internal bias regulator; connect directly to the buck converter input supply with short, low impedance paths (operating range 6 V to 115 V, abs max 120 V). |
| 3 | EN/UVLO | input | Precision enable and UVLO programming pin: below 1.1 V rising is shutdown, between 1.1 V and 1.5 V is standby with VCC regulator on and no switching, above 1.5 V starts the start-up sequence. |
| 4 | RT | input | On-time programming pin; a resistor between this pin and GND sets the buck switch on time. |
| 5 | FB | input | Feedback input of the voltage regulation comparator. |
| 6 | PGOOD | output | Open-drain power-good indicator; connect to a source voltage through an external 10 kΩ to 100 kΩ pullup resistor, or to GND if not needed. |
| 7 | BST | power_in | Bootstrap gate-drive supply; requires a high-quality 2.2-nF X7R ceramic capacitor between BST and SW to bias the internal high-side gate driver. |
| 8 | SW | power_out | Switching node internally connected to the source of the high-side NMOS buck switch and drain of the low-side NMOS synchronous rectifier; connect to the power inductor switching node. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | SOP-8-EP |
| Category | Global Sourcing Parts |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN pin voltage | VIN | -0.3 | 120 | V | 4 | ||
| SW DC voltage | SW | -1.5 | 120 | V | DC | 4 | |
| SW transient voltage | SW | -3 | V | transient < 20 ns | 4 | ||
| BST voltage | BST | -0.3 | 125.5 | V | 4 | ||
| BST to SW voltage | BST-SW | -0.3 | 5.5 | V | 4 | ||
| EN voltage | EN | -0.3 | 120 | V | 4 | ||
| FB voltage | FB | -0.3 | 5.5 | V | 4 | ||
| RT voltage | RT | -0.3 | 5.5 | V | 4 | ||
| PGOOD voltage | PGOOD | -0.3 | 14 | V | 4 | ||
| External BST to SW capacitance | CBST | 2.5 | nF | FPWM and fly-buck operation | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM, ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD CDM | V(ESD) | -500 | 500 | V | CDM, ANSI/ESDA/JEDEC JS-002 | 4 | |
| VIN pin voltage | VIN | 6 | 115 | V | 4 | ||
| EN pin voltage | VEN | 115 | V | 4 | |||
| Output current range | IOUT | 0.65 | A | LM5169 | 4 | ||
| External BST to SW capacitance | CBST | 2.2 | nF | FPWM Mode | 4 | ||
| Switching frequency | FSW | 100 | 1000 | kHz | 4 | ||
| Junction-to-ambient thermal resistance (EVM) | RθJA(EVM) | 22 | °C/W | LM5168PEVM | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 38.9 | °C/W | DDA (SOIC) 8 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 51.7 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 2.9 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 14.1 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 14.1 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.3 | °C/W | 5 | |||
| VIN quiescent current, PWM | IQ(VIN) | 420 | 880 | µA | VEN = 2.5 V, PWM Operation | 5 | |
| VIN quiescent current, PFM | IQ(VIN) | 10 | 25 | µA | VEN = 2.5 V, PFM Operation | 5 | |
| VIN standby current - LDO only | IQ(STANDBY) | 17 | 35 | µA | VEN = 1.25 V | 5 | |
| VIN shutdown supply current | ISD(VIN) | 3 | 6 | µA | VEN = 0 V, Tj=25°C | 5 | |
| EN voltage rising threshold | VEN(R) | 1.45 | 1.5 | 1.55 | V | EN rising, enable switching | 5 |
| EN voltage falling threshold | VEN(F) | 1.35 | 1.4 | 1.44 | V | EN falling, disable switching | 5 |
| EN standby rising threshold | VSD(R) | 1.1 | V | EN rising, enable internal LDO, no switching. | 5 | ||
| EN standby falling threshold | VSD(F) | 0.45 | V | EN falling, disable internal LDO. | 5 | ||
| FB voltage | VFB | 1.181 | 1.2 | 1.218 | V | VFB falling | 5 |
| Internal fixed soft-start time | tSS | 1.75 | 3 | 4.75 | ms | 5 | |
| High-side MOSFET on-resistance | RDSON(HS) | 1.91 | Ω | ISW = -100 mA | 5 | ||
| Low-side MOSFET on-resistance | RDSON(LS) | 0.74 | Ω | ISW = 100 mA | 5 | ||
| Minimum ON pulse width | tON(min) | 50 | ns | 5 | |||
| Minimum OFF pulse width | tOFF(min) | 50 | ns | 5 | |||
| BOOT-SW UVLO rising threshold | VBOOT-SW(UV_R) | 2.6 | 3.4 | V | VBOOT-SW rising | 5 | |
| High-side peak current limit | IHS_PK(OC) | 0.71 | 0.84 | 0.94 | A | LM5169 | 5 |
| Low-side peak current limit | ILS_PK(OC) | 0.71 | 0.84 | 0.94 | A | LM5169 | 5 |
| Min of IHS_PK(OC) or ILS_PK(OC) minus ILS_V(OC) | IDELTA(OC) | 0.168 | A | LM5169 | 5 | ||
| Low-side negative current limit | ILS(NOC) | 1.05 | 1.5 | 1.9 | A | LM5169 | 6 |
| Low-side valley current limit | ILS_V(OC) | 0.569 | 0.672 | 0.775 | A | LM5169, Low-side valley current limit on LS FET | 6 |
| Zero-cross detection current threshold | IZC | 0 | A | 6 | |||
| Hiccup time before re-start | TW | 64 | ms | 6 | |||
| Power Good threshold, falling | VPGTH | 1.055 | 1.08 | 1.1 | V | FB falling, PG high to low | 6 |
| Power Good threshold, rising | VPGTH | 1.105 | 1.14 | 1.175 | V | FB rising, PG low to high | 6 |
| Power Good on-resistance | RPG | 7 | Ω | VFB = 1 V | 6 | ||
| Thermal shutdown threshold | TJ(SD) | 175 | °C | Temperature rising | 6 | ||
| Thermal shutdown hysteresis | TJ(HYS) | 10 | °C | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and connect to a large copper plane to reduce thermal resistance. | 3 |
CAD (KiCad official)
- Symbol:
LM5169PDDAR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
lm5169pddar-etched.step/lm5169pddar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5169pddar.step/lm5169pddar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TEXAS INSTRUMENTS datasheet (50 pp, sha256
52a2e1a99ddd4bee, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).