component
LM5163QDDARQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownLM5163QDDARQ1
Texas Instruments · DC-DC Converters · SO-8
LM5163QDDARQ1 from Texas Instruments, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground connection for internal circuits. |
| 2 | VIN | power_in | Regulator supply input pin to the high-side power MOSFET and internal bias regulator; connect directly to the buck converter input supply with short, low impedance paths (6 V to 100 V operating, abs max 100 V). |
| 3 | EN/UVLO | input | Precision enable and UVLO programming pin: below 1.1 V the converter is in shutdown, between 1.1 V and 1.5 V it is in standby with VCC regulator operational and no switching, above 1.5 V start-up begins. |
| 4 | RON | input | On-time programming pin; a resistor between this pin and GND sets the buck switch on-time. |
| 5 | FB | input | Feedback input of the voltage regulation comparator. |
| 6 | PGOOD | output | Open-drain power good indicator; connect to a source voltage through an external pullup resistor between 10 kΩ and 100 kΩ. |
| 7 | BST | power_in | Bootstrap gate-drive supply; requires a high-quality 2.2-nF 50-V X7R ceramic capacitor between BST and SW to bias the internal high-side gate driver. |
| 8 | SW | power_out | Switching node internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier; connect to the power inductor switching node. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-8 |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND | VIN | -0.3 | 100 | V | 4 | ||
| EN to GND | EN | -0.3 | 100 | V | 4 | ||
| FB to GND | FB | -0.3 | 5.5 | V | 4 | ||
| RON to GND | RON | -0.3 | 5.5 | V | 4 | ||
| External BST to SW capacitance | CBST | 1.5 | 2.5 | nF | 4 | ||
| BST to GND | -0.3 | 105.5 | V | 4 | |||
| BST to SW | -0.3 | 5.5 | V | 4 | |||
| SW to GND | -1.5 | 100 | V | 4 | |||
| SW to GND (20-ns transient) | -3 | V | 20-ns transient | 4 | |||
| PGOOD to GND | -0.3 | 14 | V | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM, all pins | 4 | |
| ESD CDM | V(ESD) | -500 | 500 | V | All pins except 1, 4, 5, and 8 | 4 | |
| ESD CDM | V(ESD) | -750 | 750 | V | Pins 1, 4, 5, and 8 | 4 | |
| Input voltage | VIN | 6 | 100 | V | 4 | ||
| Switch node voltage | VSW | 100 | V | 4 | |||
| Enable voltage | VEN/UVLO | 100 | V | 4 | |||
| Load current | ILOAD | 0.5 | 0.6 | A | 4 | ||
| Switching frequency | FSW | 1000 | kHz | 4 | |||
| External BST to SW capacitance | CBST | 2.2 | nF | 4 | |||
| Programmable on-time | tON | 50 | 10000 | ns | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 43.4 | °C/W | DDA, 8 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 59.5 | °C/W | DDA, 8 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 16.1 | °C/W | DDA, 8 pins | 5 | ||
| Junction-to-top characterization parameter | ΨJT | 4 | °C/W | DDA, 8 pins | 5 | ||
| Junction-to-board characterization parameter | ΨJB | 16.3 | °C/W | DDA, 8 pins | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.9 | °C/W | DDA, 8 pins | 5 | ||
| VIN shutdown current | IQ-SHUTDOWN | 3 | 15 | µA | VEN = 0 V | 5 | |
| VIN sleep current | IQ-SLEEP1 | 10.5 | 25 | µA | VEN = 2.5 V, VFB = 1.5 V | 5 | |
| VIN active current | IQ-ACTIVE | 600 | 880 | µA | VEN = 2.5 V | 5 | |
| Shutdown threshold rising | VSD-RISING | 1.1 | V | VEN/UVLO rising | 5 | ||
| Shutdown threshold falling | VSD-FALLING | 0.45 | V | VEN/UVLO falling | 5 | ||
| Enable threshold rising | VEN-RISING | 1.45 | 1.5 | 1.55 | V | VEN/UVLO rising | 5 |
| Enable threshold falling | VEN-FALLING | 1.35 | 1.4 | 1.44 | V | VEN/UVLO falling | 5 |
| FB regulation voltage | VREF | 1.181 | 1.2 | 1.218 | V | VFB falling | 5 |
| On-time1 | tON1 | 5000 | ns | VVIN = 6 V, RRON = 75 kΩ | 5 | ||
| On-time2 | tON2 | 1650 | ns | VVIN = 6 V, RRON = 25 kΩ | 5 | ||
| On-time3 | tON3 | 2550 | ns | VVIN = 12 V, RRON = 75 kΩ | 5 | ||
| On-time4 | tON4 | 830 | ns | VVIN = 12 V, RRON = 25 kΩ | 5 | ||
| FB upper threshold for PGOOD high to low | VPG-UTH | 1.105 | 1.14 | 1.175 | V | VFB rising | 5 |
| FB lower threshold for PGOOD high to low | VPG-LTH | 1.055 | 1.08 | 1.1 | V | VFB falling | 5 |
| PGOOD threshold hysteresis | VPG-HYS | 60 | mV | VFB falling | 5 | ||
| PGOOD pulldown resistance | RPG | 30 | Ω | VFB = 1 V | 5 | ||
| Gate drive UVLO | VBST-UV | 2.7 | 3.4 | V | VBST rising | 5 | |
| High-side MOSFET RDSON | RDSON-HS | 0.725 | Ω | ISW = -100 mA | 5 | ||
| Low-side MOSFET RDSON | RDSON-LS | 0.33 | Ω | ISW = 100 mA | 5 | ||
| Internal soft-start time | tSS | 1.75 | 3 | 4.75 | ms | 6 | |
| Peak current limit threshold (HS) | IPEAK1 | 0.63 | 0.75 | 0.87 | A | 6 | |
| Peak current limit threshold (LS) | IPEAK2 | 0.63 | 0.75 | 0.87 | A | 6 | |
| Min of (IPEAK1 or IPEAK2) minus IVALLEY | IDELTA-ILIM | 100 | mA | 6 | |||
| Valley current limit threshold | IVALLEY | 0.5 | 0.6 | 0.72 | A | 6 | |
| Thermal shutdown threshold | TSD | 175 | °C | TJ rising | 6 | ||
| Thermal shutdown hysteresis | TSD-HYS | 10 | °C | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and connect to a large copper plane to reduce thermal resistance. | 3 |
CAD (KiCad official)
- Symbol:
LM5163QDDARQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
lm5163qddarq1-etched.step/lm5163qddarq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5163qddarq1.step/lm5163qddarq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
efed6596127320d7, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).