component
LM5157QRTERQ1
Public Made by Adomby adom
TEXAS INSTRUMENTS DC-DC Converters, WQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownLM5157QRTERQ1
TEXAS INSTRUMENTS · DC-DC Converters · WQFN-16(3x3)
LM5157QRTERQ1 from TEXAS INSTRUMENTS, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground pin and source connection of the internal N-channel power MOSFET. |
| 2 | VCC | power_out | Output of the internal VCC regulator and supply input of the internal MOSFET driver, requiring a 5-Ω resistor in series with a 1-µF ceramic bypass capacitor to PGND. |
| 3 | BIAS | power_in | Supply voltage input to the VCC regulator, bypassed to PGND with a capacitor. |
| 4 | PGOOD | output | Open-drain power-good indicator that goes low when FB is below the undervoltage threshold (VUVTH), requiring a pullup resistor to the system rail. |
| 5 | RT | input | Switching frequency setting pin, programmed by a single resistor between RT and AGND. |
| 6 | UVLO/SYNC/EN | input | Enable pin that shuts the converter down when below the enable threshold (VEN), also used for programmable UVLO (must not be left floating, connect to BIAS if unused) and external clock synchronization via a negative pulse input. |
| 7 | AGND | power_in | Analog ground pin, to be connected to the analog ground plane through a wide and short path. |
| 8 | COMP | output | Output of the internal transconductance error amplifier, with loop compensation components connected between this pin and AGND. |
| 9 | FB | input | Inverting input of the error amplifier, fed by a voltage divider that sets the output voltage in boost, SEPIC, or primary-side regulated flyback topologies, with the low-side resistor close to AGND. |
| 10 | SS | input | Soft-start time programming pin, where an external capacitor and internal current source set the error amplifier reference ramp rate, with the capacitor ground returned to AGND. |
| 11 | MODE | input | Mode selection pin, sampled at initial power-up to set hiccup protection and spread spectrum via 0 V/AGND, 37.4 kΩ, 62.0 kΩ, or 100 kΩ resistor (or 370 mV, 620 mV, >1 V levels). |
| 12 | SW | output | Switch pin and drain connection of the internal N-channel power MOSFET. |
| 13 | SW | output | Switch pin and drain connection of the internal N-channel power MOSFET. |
| 14 | SW | output | Switch pin and drain connection of the internal N-channel power MOSFET. |
| 15 | NC | unconnected | No internal electrical contact; optionally connect to PGND for improved thermal conductivity. |
| 16 | PGND | power_in | Power ground pin and source connection of the internal N-channel power MOSFET. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | WQFN-16(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| BIAS to AGND | -0.3 | 50 | V | 7 | |||
| UVLO to AGND | -0.3 | V | Upper limit printed as VBIAS + 0.3 | 7 | |||
| SS, RT to AGND | -0.3 | 3.8 | V | 7 | |||
| FB to AGND | -0.3 | 4 | V | 7 | |||
| MODE to AGND | -0.3 | 3.8 | V | 7 | |||
| PGND to AGND | -0.3 | 0.3 | V | 7 | |||
| VCC to AGND | -0.3 | 5.8 | V | Operating lifetime de-rated when pin voltage is greater than 5.5 V | 7 | ||
| PGOOD to AGND | -0.3 | 18 | V | 7 | |||
| COMP to AGND | -0.3 | V | Internal max voltage clamp handles up to 1.6 mA; maximum not printed | 7 | |||
| SW to AGND (DC) | -0.3 | 50 | V | DC | 7 | ||
| SW to AGND (6 ns transient) | -4 | V | 6 ns transient | 7 | |||
| Junction temperature | TJ | -40 | 150 | °C | High junction temperatures degrade operating lifetimes | 7 | |
| Storage temperature | Tstg | -55 | 150 | °C | 7 | ||
| Boost converter input (when BIAS ≥ 2.9 V) | VSUPPLY | 1.5 | 45 | V | when BIAS ≥ 2.9 V | 7 | |
| Boost converter output | VLOAD | 48 | V | Boost converter output can be up to 48 V; VSUPPLY shown as the printed condition | 7 | ||
| BIAS input | VBIAS | 2.9 | 45 | V | 7 | ||
| UVLO input | VUVLO | 0 | 45 | V | 7 | ||
| FB input | VFB | 0 | 4 | V | 7 | ||
| Switch current | ISW | 0 | A | Maximum limited by ILIM; see note (4) | 7 | ||
| Typical switching frequency | fSW | 100 | 2200 | kHz | 7 | ||
| Synchronization pulse frequency | fSYNC | 100 | 2200 | kHz | 7 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 8 | ||
| BIAS shutdown current | ISHUTDOWN(BIAS) | 2.6 | 5 | μA | VBIAS = 12 V, VUVLO = 0 V | 8 | |
| BIAS operating current | IOPERATING(BIAS) | 700 | 775 | μA | VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF, RT = 220 kΩ | 8 | |
| VCC regulation | VVCC-REG | 4.66 | 4.9 | 5.14 | V | VBIAS = 8 V, IVCC = 18 mA | 8 |
| VCC UVLO threshold (rising) | VVCC-UVLO(RISING) | 2.75 | 2.8 | 2.85 | V | VCC rising | 8 |
| Enable threshold (rising) | VEN(RISING) | 0.4 | 0.52 | 0.7 | V | EN rising | 8 |
| Enable threshold (falling) | VEN(FALLING) | 0.33 | 0.49 | 0.63 | V | EN falling | 8 |
| UVLO / SYNC threshold (rising) | VUVLO(RISING) | 1.425 | 1.5 | 1.575 | V | UVLO rising | 8 |
| UVLO / SYNC threshold (falling) | VUVLO(FALLING) | 1.37 | 1.45 | 1.52 | V | UVLO falling | 8 |
| UVLO hysteresis current | IUVLO | 4 | 5 | 6 | μA | VUVLO = 1.6 V | 8 |
| FSW modulation (upper limit) | 7.8 | % | 9 | ||||
| FSW modulation (lower limit) | -7.8 | % | 9 | ||||
| Soft-start current | ISS | 9 | 10 | 11 | μA | 9 | |
| Switching frequency (RT = 220 kΩ) | fsw1 | 85 | 100 | 115 | kHz | RT = 220 kΩ | 9 |
| Switching frequency (RT = 49.3 kΩ) | fsw2 | 388 | 440 | 492 | kHz | RT = 49.3 kΩ | 9 |
| Switching frequency (RT = 9.09 kΩ) | fsw3 | 1980 | 2200 | 2420 | kHz | RT = 9.09 kΩ | 9 |
| Maximum duty cycle limit (DMAX1) | DMAX1 | 80 | 85 | 90 | % | RT = 9.09 kΩ | 9 |
| Maximum duty cycle limit (DMAX2) | DMAX2 | 90 | 93 | 96 | % | RT = 220 kΩ | 9 |
| Internal MOSFET current limit (LM5157) | ILIM | 6.5 | 7.5 | 8.5 | A | LM5157 variant | 9 |
| FB reference | VREF | 0.99 | 1 | 1.01 | V | 9 | |
| COMP clamp voltage (rising) | 2.5 | 2.8 | V | COMP rising (VUVLO = 2.0 V) | 9 | ||
| COMP clamp voltage (falling) | 1 | 1.1 | V | COMP falling | 9 | ||
| Overvoltage threshold (FB rising) | VOVTH | 107 | 110 | 113 | % | FB rising (referece to VREF) | 9 |
| Undervoltage threshold (FB falling) | VUVTH | 87 | 90 | 93 | % | FB falling (referece to VREF) | 9 |
| Internal MOSFET on-resistance (VBIAS = 12 V) | rDS(ON) | 45 | 90 | mΩ | VBIAS = 12 V | 9 | |
| Internal MOSFET on-resistance (VBIAS = 3.5 V) | rDS(ON) | 47 | 95 | mΩ | VBIAS = 3.5 V | 9 | |
| Junction-to-ambient thermal resistance | RθJA | 45.8 | °C/W | 8 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 45.3 | °C/W | 8 | |||
| Junction-to-board thermal resistance | RθJB | 20 | °C/W | 8 | |||
| Junction-to-top characterization parameter | ΨJT | 0.8 | °C/W | 8 | |||
| Junction-to-board characterization parameter | ΨJB | 20 | °C/W | 8 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 6.9 | °C/W | 8 | |||
| Junction-to-ambient thermal resistance (EVM board) | RθJA | 32.7 | °C/W | LM5157EVM-BST board | 8 | ||
| Junction-to-top characterization parameter (EVM board) | ΨJT | 0.6 | °C/W | LM5157EVM-BST board | 8 | ||
| Junction-to-board characterization parameter (EVM board) | ΨJB | 14.8 | °C/W | LM5157EVM-BST board | 8 |
CAD (KiCad official)
- Symbol:
LM5157QRTERQ1 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
lm5157qrterq1-etched.step/lm5157qrterq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5157qrterq1.step/lm5157qrterq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TEXAS INSTRUMENTS datasheet (49 pp, sha256
b17edbd026370cbb, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).