component

LM51571RTER

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, WQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lm51571rterfactory-2.0.0extractor-text

Verified LM51571RTER

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LM51571RTER · WQFN-16(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 48-page datasheet
  • ✓distributor: lcsc C3188430, digikey 296-LM51571RTERTR-ND, mouser 595-LM51571RTER
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_adwtqap/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lm51571rter.kicad_sym✓ lm51571rter.kicad_mod✓ lm51571rter.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers lm51571rter: viewers · Ray 4d ago
lm51571rter-etched.glb Publish 0.1.0 · Ray 4d ago
lm51571rter-etched.step lm51571rter: factory component page (tier=mfr) · Ray 4d ago
lm51571rter-hero.glb lm51571rter: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
lm51571rter-hero.overlay.json Publish 0.1.0 · Ray 4d ago
lm51571rter.glb Publish 0.1.0 · Ray 4d ago
lm51571rter.kicad_mod Publish 0.1.0 · Ray 4d ago
lm51571rter.kicad_sym Publish 0.1.0 · Ray 4d ago
lm51571rter.lbr Publish 0.1.0 · Ray 4d ago
lm51571rter.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier mfr, 17 pins · Ray 4d ago

LM51571RTER

Texas Instruments · DC-DC Converters · WQFN-16(3x3)

LM51571RTER from Texas Instruments, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGND power_in Power ground pin and source connection of the internal N-channel power MOSFET.
2 VCC power_out Output of the internal VCC regulator and supply input for the MOSFET driver; connect a 5-Ω resistor in series with a 1-µF ceramic bypass capacitor from this pin to PGND.
3 BIAS power_in Supply voltage input to the VCC regulator; connect a bypass capacitor from this pin to PGND.
4 PGOOD output Open-drain power-good indicator that goes low if FB is below the undervoltage threshold VUVTH; connect a pullup resistor to the system voltage rail.
5 RT input Switching frequency setting pin programmed by a single resistor between RT and AGND.
6 UVLO/SYNC/EN input Enable pin that shuts the converter down when below the enable threshold VEN, also used for UVLO programming and external synchronization; it must not be left floating and should connect to BIAS if not used.
7 AGND power_in Analog ground pin; connect to the analog ground plane through a wide and short path.
8 COMP output Output of the internal transconductance error amplifier; loop compensation components connect between this pin and AGND.
9 FB input Inverting input of the error amplifier; the low-side feedback resistor connects close to AGND.
10 SS input Soft-start time programming pin; an external capacitor and internal current source set the ramp rate of the error amplifier reference.
11 MODE input Sampled at initial power up to set hiccup mode protection and spread spectrum: 0 V or AGND disables both, 370 mV (37.4 kΩ) enables both, 620 mV (62.0 kΩ) enables hiccup only, and above 1 V (100 kΩ) enables spread spectrum only.
12 SW passive Switch pin, the drain connection of the internal N-channel power MOSFET.
13 SW passive Switch pin, the drain connection of the internal N-channel power MOSFET.
14 SW passive Switch pin, the drain connection of the internal N-channel power MOSFET.
15 NC unconnected No internal electrical contact; optionally connect to PGND for improved thermal conductivity.
16 PGND power_in Power ground pin and source connection of the internal N-channel power MOSFET.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-16(3x3)
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
BIAS to AGND -0.3 50 V 6
UVLO to AGND -0.3 V max VBIAS + 0.3 V as printed 6
SS, RT to AGND -0.3 3.8 V 6
FB to AGND -0.3 4 V 6
MODE to AGND -0.3 3.8 V 6
PGND to AGND -0.3 0.3 V 6
VCC to AGND -0.3 5.8 V 6
PGOOD to AGND -0.3 18 V 6
COMP to AGND -0.3 V 6
SW to AGND (DC) -0.3 50 V DC 6
SW to AGND (6-ns transient) -4 V 6-ns transient 6
Junction temperature TJ -40 150 °C 6
Storage temperature Tstg -55 150 °C 6
Electrostatic discharge, human body model V(ESD) -2000 2000 V HBM, per ANSI/ESDA/JEDEC JS-001, all pins 6
Electrostatic discharge, charged device model V(ESD) -500 500 V CDM, per JEDEC JESD22-C101, all pins 6
Boost converter input supply VSUPPLY 1.5 45 V Boost converter input (when BIAS ≥ 2.9 V) 6
Boost converter output VLOAD 48 V Boost converter output, see note 2 6
BIAS input VBIAS 2.9 45 V see note 3 6
UVLO input VUVLO 0 45 V 6
FB input VFB 0 4 V 6
Switch current ISW 0 A see note 4 6
Typical switching frequency fSW 100 2200 kHz 6
Synchronization pulse frequency fSYNC 100 2200 kHz 6
Operating junction temperature TJ -40 125 °C 6
BIAS shutdown current ISHUTDOWN(BIAS) 2.6 5 μA VBIAS = 12 V, VUVLO = 0 V 7
BIAS operating current IOPERATING(BIAS) 700 850 μA VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF, RT = 220 kΩ 7
VCC regulation VVCC-REG 4.66 4.9 5.14 V VBIAS = 8 V, IVCC = 18 mA 7
VCC UVLO threshold VVCC-UVLO(RISING) 2.75 2.8 2.85 V VCC rising 7
Enable threshold, EN rising VEN(RISING) 0.4 0.52 0.7 V EN rising 7
Enable threshold, EN falling VEN(FALLING) 0.33 0.49 0.63 V EN falling 7
UVLO / SYNC threshold, rising VUVLO(RISING) 1.425 1.5 1.575 V UVLO rising 7
UVLO / SYNC threshold, falling VUVLO(FALLING) 1.37 1.45 1.52 V UVLO falling 7
UVLO hysteresis current IUVLO 4 5 6 μA VUVLO = 1.6 V 7
FSW modulation (upper limit) 7.8 % Spread spectrum, upper limit 7
FSW modulation (lower limit) -7.8 % Spread spectrum, lower limit 7
Soft-start current ISS 9 10 11 μA 8
Switching frequency fsw1 85 100 115 kHz RT = 220 kΩ 8
Switching frequency fsw2 388 440 492 kHz RT = 49.3 kΩ 8
Switching frequency fsw3 1980 2200 2420 kHz RT = 9.09 kΩ 8
Maximum duty cycle limit DMAX1 80 85 90 % RT = 9.09 kΩ 8
Maximum duty cycle limit DMAX2 90 93 96 % RT = 220 kΩ 8
Internal MOSFET current limit ILIM 4.33 5 5.67 A LM51571 option 8
FB reference VREF 0.99 1 1.01 V 8
COMP clamp voltage, rising 2.5 2.8 V COMP rising (VUVLO = 2.0 V) 8
COMP clamp voltage, falling 1 1.1 V COMP falling 8
Overvoltage threshold, FB rising VOVTH 107 110 113 % FB rising (referece to VREF) 8
Undervoltage threshold, FB falling VUVTH 87 90 93 % FB falling (referece to VREF) 8
Internal MOSFET on-resistance rDS(ON) 45 90 mΩ VBIAS = 12 V 8
Internal MOSFET on-resistance rDS(ON) 47 95 mΩ VBIAS = 3.5 V 8
Junction-to-ambient thermal resistance RθJA 44.4 °C/W 7
Junction-to-case (top) thermal resistance RθJC(top) 42.1 °C/W 7
Junction-to-board thermal resistance RθJB 17.3 °C/W 7
Junction-to-top characterization parameter ΨJT 0.8 °C/W 7
Junction-to-board characterization parameter ΨJB 17.3 °C/W 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 6.7 °C/W 7

CAD (KiCad official)

  • Symbol: LM51571RTER
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: lm51571rter-etched.step / lm51571rter-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm51571rter.step / lm51571rter.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 fa0ec9869788c576, retrieved 2026-11-02, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF