# LM51571QRTERQ1

**TEXAS INSTRUMENTS** · Global Sourcing Parts · WQFN-16(3x3)

LM51571QRTERQ1 from TEXAS INSTRUMENTS, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground pin and source connection of the internal N-channel power MOSFET. |
| 2 | VCC | power_out | Output of the internal VCC regulator and supply input of the internal MOSFET driver; connect a 5-Ω resistor in series with a 1-µF ceramic bypass capacitor from this pin to PGND. |
| 3 | BIAS | power_in | Supply voltage input to the VCC regulator (2.9 V to 45 V recommended, 50 V abs max); connect a bypass capacitor from this pin to PGND. |
| 4 | PGOOD | output | Open-drain power-good indicator that goes low if FB is below the undervoltage threshold (VUVTH); connect a pullup resistor to the system voltage rail. |
| 5 | RT | input | Switching frequency setting pin, programmed by a single resistor between RT and AGND. |
| 6 | UVLO/SYNC/EN | input | Enable, programmable line UVLO divider input and external synchronization clock input (negative pulse); converter shuts down below the enable threshold (VEN), must not be left floating, and connects to BIAS if not used. |
| 7 | AGND | power_in | Analog ground pin; connect to the analog ground plane through a wide and short path. |
| 8 | COMP | output | Output of the internal transconductance error amplifier; connect the loop compensation components between this pin and AGND. |
| 9 | FB | input | Inverting input of the error amplifier; connect a voltage divider to set the output voltage, with the low-side resistor close to AGND. |
| 10 | SS | input | Soft-start time programming pin; an external capacitor and an internal current source set the reference ramp rate, with the capacitor ground connected to AGND. |
| 11 | MODE | input | Selects hiccup mode protection and spread spectrum at initial power up: 0 V disables both, 370 mV (37.4 kΩ) enables both, 620 mV (62.0 kΩ) hiccup only, >1 V (100 kΩ) spread spectrum only. |
| 12 | SW | passive | Switch pin, drain connection of the internal N-channel power MOSFET. |
| 13 | SW | passive | Switch pin, drain connection of the internal N-channel power MOSFET. |
| 14 | SW | passive | Switch pin, drain connection of the internal N-channel power MOSFET. |
| 15 | NC | unconnected | No internal electrical contact; optionally connect to PGND for improved thermal conductivity. |
| 16 | PGND | power_in | Power ground pin and source connection of the internal N-channel power MOSFET. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | WQFN-16(3x3) |
| Category | Global Sourcing Parts |
| Pins | 17 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| BIAS shutdown current | ISHUTDOWN(BIAS) |  | 2.6 | 5 | μA | VBIAS = 12 V, VUVLO = 0 V | 8 |
| BIAS operating current | IOPERATING(BIAS) |  | 700 | 775 | μA | VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF, RT = 220 kΩ | 8 |
| VCC regulation | VVCC-REG | 4.66 | 4.9 | 5.14 | V | VBIAS = 8 V, IVCC = 18 mA | 8 |
| VCC UVLO threshold | VVCC-UVLO(RISING) | 2.75 | 2.8 | 2.85 | V | VCC rising | 8 |
| Enable threshold rising | VEN(RISING) | 0.4 | 0.52 | 0.7 | V | EN rising | 8 |
| Enable threshold falling | VEN(FALLING) | 0.33 | 0.49 | 0.63 | V | EN falling | 8 |
| UVLO threshold rising | VUVLO(RISING) | 1.425 | 1.5 | 1.575 | V | UVLO rising | 8 |
| UVLO threshold falling | VUVLO(FALLING) | 1.37 | 1.45 | 1.52 | V | UVLO falling | 8 |
| UVLO hysteresis current | IUVLO | 4 | 5 | 6 | μA | VUVLO = 1.6 V | 8 |
| Soft-start current | ISS | 9 | 10 | 11 | μA |  | 9 |
| Switching frequency 1 | fsw1 | 85 | 100 | 115 | kHz | RT = 220 kΩ | 9 |
| Switching frequency 2 | fsw2 | 388 | 440 | 492 | kHz | RT = 49.3 kΩ | 9 |
| Switching frequency 3 | fsw3 | 1980 | 2200 | 2420 | kHz | RT = 9.09 kΩ | 9 |
| Maximum duty cycle limit 1 | DMAX1 | 80 | 85 | 90 | % | RT = 9.09 kΩ | 9 |
| Maximum duty cycle limit 2 | DMAX2 | 90 | 93 | 96 | % | RT = 220 kΩ | 9 |
| Internal MOSFET current limit LM51571 | ILIM | 4.33 | 5 | 5.67 | A | LM51571 | 9 |
| FB reference | VREF | 0.99 | 1 | 1.01 | V |  | 9 |
| COMP clamp voltage rising |  |  | 2.5 | 2.8 | V | COMP rising (VUVLO = 2.0 V) | 9 |
| COMP clamp voltage falling |  |  | 1 | 1.1 | V | COMP falling | 9 |
| Overvoltage threshold rising | VOVTH | 107 | 110 | 113 | % | FB rising (reference to VREF) | 9 |
| PGOOD pulldown RDSON |  |  |  | 70 | Ω | 1 mA sinking | 9 |
| Undervoltage threshold falling | VUVTH | 87 | 90 | 93 | % | FB falling (reference to VREF) | 9 |
| MOSFET on-resistance | rDS(ON) |  | 45 | 90 | mΩ | VBIAS = 12 V | 9 |
| MOSFET on-resistance | rDS(ON) |  | 47 | 95 | mΩ | VBIAS = 3.5 V | 9 |
| Switch leakage current |  |  |  | 1200 | nA | VSW = 12 V | 9 |
| Thermal shutdown threshold | TTSD |  | 175 |  | °C | Temperature rising | 9 |
| BIAS to AGND |  | -0.3 |  | 50 | V |  | 7 |
| UVLO to AGND |  | -0.3 |  |  | V | max VBIAS + 0.3 | 7 |
| SS, RT to AGND |  | -0.3 |  | 3.8 | V |  | 7 |
| FB to AGND |  | -0.3 |  | 4 | V |  | 7 |
| MODE to AGND |  | -0.3 |  | 3.8 | V |  | 7 |
| PGND to AGND |  | -0.3 |  | 0.3 | V |  | 7 |
| VCC to AGND |  | -0.3 |  | 5.8 | V |  | 7 |
| PGOOD to AGND |  | -0.3 |  | 18 | V |  | 7 |
| SW to AGND (DC) |  | -0.3 |  | 50 | V |  | 7 |
| SW to AGND transient |  | -4 |  |  | V | 6 ns transient | 7 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 7 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 7 |
| Boost converter input | VSUPPLY | 1.5 |  | 45 | V | when BIAS ≥ 2.9V | 7 |
| Boost converter output | VLOAD |  |  | 48 | V | min is VSUPPLY | 7 |
| BIAS input | VBIAS | 2.9 |  | 45 | V |  | 7 |
| UVLO input | VUVLO | 0 |  | 45 | V |  | 7 |
| FB input | VFB | 0 |  | 4 | V |  | 7 |
| Typical switching frequency | fSW | 100 |  | 2200 | kHz |  | 7 |
| Synchronization pulse frequency | fSYNC | 100 |  | 2200 | kHz |  | 7 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 8 |
| Junction-to-ambient thermal resistance | RθJA |  | 45.8 |  | °C/W | RTE (QFN) 16 pins | 8 |
| Junction-to-ambient thermal resistance (EVM) | RθJA |  | 32.7 |  | °C/W | LM5157EVM-BST | 8 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 45.3 |  | °C/W |  | 8 |
| Junction-to-board thermal resistance | RθJB |  | 20 |  | °C/W |  | 8 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 6.9 |  | °C/W |  | 8 |
| HBM ESD | V(ESD) | -2000 |  | 2000 | V | HBM, AEC Q100-002 | 7 |
| CDM ESD all pins | V(ESD) | -500 |  | 500 | V | CDM, AEC Q100-011, all pins | 7 |

## CAD (KiCad official)

- Symbol: `LM51571QRTERQ1`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `lm51571qrterq1-etched.step` / `lm51571qrterq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm51571qrterq1.step` / `lm51571qrterq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TEXAS INSTRUMENTS datasheet](https://www.ti.com/cn/lit/gpn/lm51571-q1) (49 pp, sha256 `b17edbd026370cbb`, retrieved 2026-10-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lm51571qrterq1-datasheet.pdf)