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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LM5140QRWGTQ1

Texas Instruments · DC-DC Controllers · VQFN-40-EP(6x6)

LM5140QRWGTQ1 from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SS2	input	Channel 2 soft-start ramp node; internal 20-μA source charges external capacitor; pulling below 80 mV disables channel 2 gate driver outputs.
2	COMP2	output	Channel 2 transconductance error amplifier output; apply compensation network to set loop response.
3	FB2	input	Channel 2 feedback input; connect to VDDA for 5-V output, ground for 8-V fixed output, or external divider for 1.5-15-V adjustable (1.2-V regulation threshold).
4	CS2	input	Channel 2 current sense amplifier input; make low-current Kelvin connection to inductor side of sense resistor.
5	VOUT2	input	Channel 2 output and current sense amplifier input; connect to load side of channel 2 current sense resistor.
6	VCCX	input	Optional external 5-V bias supply input; if VCCX > 4.5 V, internally connected to VCC and disables internal regulator; ground if unused; maximum 6.5 V.
7	PG2	output	Channel 2 power-good open-collector output; asserts low when VOUT2 falls below 92% or rises above 110% of regulation voltage; 25-μs deglitch filter.
8	HOL2	output	Channel 2 high-side gate driver turn-off output; independent source/sink pin for adjustable slew-rate control.
9	HO2	output	Channel 2 high-side gate driver turn-on output; sources 3.25-A peak current at HB2 voltage, sinks 4.25 A peak.
10	SW2	input	Channel 2 switching node sense input; connect to bootstrap capacitor, source of high-side MOSFET, and drain of low-side MOSFET.
11	HB2	output	Channel 2 bootstrap gate driver supply output; charges from VCC through external diode when low-side FET is on; typical voltage HB2 - SW2 = 4.5-5.25 V.
12	LOL2	output	Channel 2 low-side gate driver turn-off output; independent source/sink pin for adjustable slew-rate control.
13	LO2	output	Channel 2 low-side gate driver turn-on output; sources 3.25-A peak current, sinks 4.25 A peak to PGND.
14	PGND2	power_in	Channel 2 power ground return for low-side MOSFET gate driver; connect to board power ground plane.
15	VCC	power_in	Bias supply input (pins 15 and 16 must be connected together on PCB); 5-V regulated output (4.75-5.25 V typical); 150-mA minimum source limit.
16	VCC	power_in	Bias supply input (pins 15 and 16 must be connected together on PCB); 5-V regulated output (4.75-5.25 V typical); 150-mA minimum source limit.
17	PGND1	power_in	Channel 1 power ground return for low-side MOSFET gate driver; connect to board power ground plane.
18	LO1	output	Channel 1 low-side gate driver turn-on output; sources 3.25-A peak current, sinks 4.25 A peak to PGND.
19	LOL1	output	Channel 1 low-side gate driver turn-off output; independent source/sink pin for adjustable slew-rate control.
20	HB1	output	Channel 1 bootstrap gate driver supply output; charges from VCC through external diode when low-side FET is on; typical voltage HB1 - SW1 = 4.5-5.25 V.
21	SW1	input	Channel 1 switching node sense input; connect to bootstrap capacitor, source of high-side MOSFET, and drain of low-side MOSFET.
22	HO1	output	Channel 1 high-side gate driver turn-on output; sources 3.25-A peak current at HB1 voltage, sinks 4.25 A peak.
23	HOL1	output	Channel 1 high-side gate driver turn-off output; independent source/sink pin for adjustable slew-rate control.
24	PG1	output	Channel 1 power-good open-collector output; asserts low when VOUT1 falls below 92% or rises above 110% of regulation voltage; 25-μs deglitch filter.
25	VIN	power_in	Supply voltage input (3.8-65 V nominal, 70-V absolute maximum); provides input for internal VCC regulator; bypass with quality capacitors to minimize transient ringing.
26	VOUT1	input	Channel 1 output and current sense amplifier input; connect to load side of channel 1 current sense resistor.
27	CS1	input	Channel 1 current sense amplifier input; make low-current Kelvin connection to inductor side of sense resistor.
28	FB1	input	Channel 1 feedback input; connect to VDDA for 3.3-V output, ground for 5-V fixed output, or external divider for 1.5-15-V adjustable (1.2-V regulation threshold).
29	COMP1	output	Channel 1 transconductance error amplifier output; apply compensation network to set loop response.
30	SS1	input	Channel 1 soft-start ramp node; internal 20-μA source charges external capacitor; pulling below 80 mV disables channel 1 gate driver outputs.
31	EN1	input	Channel 1 enable logic input (active high); threshold 2.4 V typical; accepts voltage up to 70 V for wide input range applications.
32	RES	output	Restart timer output node; external capacitor configures hiccup mode off-time (20-μA internal charging current); connect to VDDA to disable hiccup protection.
33	DEMB	input	Diode emulation mode control; ground enables diode emulation mode (discontinuous conduction at light load), VDDA enables forced-PWM mode (continuous conduction).
34	ILSET	input	Current-limit threshold selection pin (latched at power-up); VDDA sets 73-mV limit, ground sets 48-mV limit; ±10% accuracy typical.
35	AGND	power_in	Analog ground return for internal voltage reference and analog circuits; connect to PGND at single point under IC for low noise.
36	VDDA	power_in	Internal analog bias regulator output (5-V nominal or 3.3-V in low-power modes); bypass with 100-nF or larger ceramic capacitor to AGND.
37	OSC	input	Oscillator frequency selection pin (latched at power-up); VDDA selects 2.2-MHz operation, ground selects 440-kHz operation; ±7% frequency tolerance.
38	SYNIN	input	External synchronization clock input (TTL level); enables internal oscillator sync to external clock; ground if synchronization feature not used.
39	SYNOUT	output	Synchronization clock output (TTL level); 180° out-of-phase with HO1 gate drive; 50% duty cycle; operates at CLK2 frequency.
40	EN2	input	Channel 2 enable logic input (active high); threshold 2.4 V typical; accepts voltage up to 70 V for wide input range applications.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-40-EP(6x6)
Category	Power Supply Chip
Pins	41

CAD (KiCad official)

Symbol: LM5140QRWGTQ1
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
3D model files: lm5140qrwgtq1-etched.step / lm5140qrwgtq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5140qrwgtq1.step / lm5140qrwgtq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (48 pp, sha256 0d277fa180b6852d, retrieved 2026-09-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF