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LM5140QRWGRQ1

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Texas Instruments DC-DC Controllers, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM5140QRWGRQ1

Texas Instruments · DC-DC Controllers · VQFN-40-EP(6x6)

LM5140QRWGRQ1 from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SS2 input Channel 2 soft-start programming pin; an external capacitor and internal 20-μA source set the error amplifier reference ramp, and pulling SS below 80 mV turns off the channel 2 gate driver outputs.
2 COMP2 output Output of the channel 2 transconductance error amplifier.
3 FB2 input Channel 2 feedback input with a 1.2 V regulation threshold; connect to VDD for a 5 V output or to ground for a fixed 8 V output, or use a resistive divider from VOUT2 to set 1.5 V to 15 V.
4 CS2 input Channel 2 current sense amplifier input, to be connected with a low-current Kelvin connection to the inductor side of the external current sense resistor.
5 VOUT2 input Channel 2 output voltage and current sense amplifier input, connected to the output side of the channel 2 current sense resistor.
6 VCCX input Optional external bias supply input; when VCCX is above 4.5 V it is connected internally to VCC and the internal VCC regulator is disabled, and it should be grounded if unused.
7 PG2 output Open-collector power-good output that goes low when VOUT2 is outside its specified regulation window.
8 HOL2 output Channel 2 high-side gate driver turn-off output.
9 HO2 output Channel 2 high-side gate driver turn-on output.
10 SW2 input Channel 2 buck switching node, connected to the bootstrap capacitor, the high-side MOSFET source and the low-side MOSFET drain.
11 HB2 output Channel 2 high-side driver supply for bootstrap gate drive.
12 LOL2 output Channel 2 low-side gate driver turn-off output.
13 LO2 output Channel 2 low-side gate driver turn-on output.
14 PGND2 power_in Power ground connection for the channel 2 low-side NMOS gate driver.
15 VCC power_out VCC bias supply pin; pin 15 and pin 16 must be connected together on the PCB.
16 VCC power_out VCC bias supply pin; pin 15 and pin 16 must be connected together on the PCB.
17 PGND1 power_in Power ground connection for the channel 1 low-side NMOS gate driver.
18 LO1 output Channel 1 low-side gate driver turn-on output.
19 LOL1 output Channel 1 low-side gate driver turn-off output.
20 HB1 output Channel 1 high-side driver supply for bootstrap gate drive.
21 SW1 input Channel 1 buck switching node, connected to the bootstrap capacitor, the high-side MOSFET source and the low-side MOSFET drain.
22 HO1 output Channel 1 high-side gate driver turn-on output.
23 HOL1 output Channel 1 high-side gate driver turn-off output.
24 PG1 output Open-collector power-good output that goes low when VOUT1 is outside its specified regulation window.
25 VIN power_in Supply voltage input source for the VCC regulators (absolute maximum 70 V on VIN per the Absolute Maximum Ratings).
26 VOUT1 input Channel 1 output voltage and current sense amplifier input, connected to the output side of the channel 1 current sense resistor.
27 CS1 input Channel 1 current sense amplifier input, to be connected with a low-current Kelvin connection to the inductor side of the external current sense resistor.
28 FB1 input Channel 1 feedback input with a 1.2 V regulation threshold; connect to VDDA for a 3.3 V output or to ground for a 5 V output, or use a resistive divider from VOUT1 to set 1.5 V to 15 V.
29 COMP1 output Output of the channel 1 transconductance error amplifier.
30 SS1 input Channel 1 soft-start programming pin; an external capacitor and internal 20 μA source set the error amplifier reference ramp, and pulling SS below 80 mV turns off the channel 1 gate driver outputs.
31 EN1 input Active-high logic input that enables channel 1.
32 RES output Restart timer pin; an external capacitor sets the hiccup-mode off time, and connecting RES to VDD during power-up disables hiccup protection.
33 DEMB input Diode emulation pin; grounding it enables diode emulation, and connecting it to VDDA operates the device in FPWM mode with continuous conduction at light loads.
34 ILSET input Current limit threshold pin; connecting to VDDA sets the current limit to 73 mV for both channels, and connecting to GND sets it to 48 mV.
35 AGND power_in Analog ground connection and return for the internal voltage reference and analog circuits.
36 VDDA power_out Internal analog bias regulator output; connect a capacitor from VDDA to AGND.
37 OSC input Frequency selection pin; connecting to VDDA selects the default 2.2 MHz oscillator frequency, and connecting to ground sets 440 kHz.
38 SYNIN input Sync input for synchronizing the internal oscillator to an external clock; connect to AGND if the synchronization feature is not used.
39 SYNOUT output TTL-level sync output signal that is 180° out of phase with the channel 1 HO1 gate drive.
40 EN2 input Active-high logic input that enables channel 2.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Power Supply Chip
Pins 41

CAD (KiCad official)

  • Symbol: LM5140QRWGRQ1
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: lm5140qrwgrq1-etched.step / lm5140qrwgrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5140qrwgrq1.step / lm5140qrwgrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 0d277fa180b6852d, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF