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LM5123QRGRRQ1

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Texas Instruments DC-DC Converters, VQFN-20(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lm5123qrgrrq1factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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LM5123QRGRRQ1

Texas Instruments · DC-DC Converters · VQFN-20(3.5x3.5)

LM5123QRGRRQ1 from Texas Instruments, in a VQFN-20(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CSP input Current sensing amplifier positive input pin for inductor current feedback with 0.8V to 42V operating range.
2 CSN input Current sensing amplifier negative input pin with 60mV peak current limiting threshold and 0.8V to 42V maximum rating.
3 VOUT/SENSE input Output voltage sensing pin for internal feedback divider requiring 0.1µF bypass capacitor with 5V to 57V operating range.
4 PGOOD tri_state Open-drain power good indicator output pin with 5kΩ to 100kΩ external pull-up resistor transitioning on output voltage under-voltage threshold.
5 HO output High side gate driver output sourcing 2.2A peak and sinking 3.3A peak current directly to high-side N-channel MOSFET gate.
6 SW passive Synchronous boost switch node connection between high and low-side MOSFETs providing dynamic switching operation and voltage sensing.
7 HB passive Bootstrap driver supply pin charged from VCC through internal bootstrap diode requiring 0.1µF capacitor between HB and SW.
8 BIAS power_in VCC regulator power supply input accepting 3.8V to 42V range with 1µF bypass capacitor supporting 0.8V minimum boost input when BIAS ≥ 3.8V.
9 VCC power_out Internal regulated 5V power supply output (4.75V to 5.25V) requiring 4.7µF bypass capacitor and 100mA minimum pull current during device configuration.
10 PGND power_in Power ground pin for low-side N-channel MOSFET source requiring short low-impedance path to ground plane.
11 LO output Low side gate driver output sourcing 2.2A peak and sinking 3.3A peak current with adaptive dead-time control to low-side MOSFET gate.
12 MODE input Switching mode selection pin configured at startup for skip mode (open or >500kΩ to AGND), diode emulation mode (<0.4V), or FPWM mode (>2.0V/VCC) with dynamic mode switching.
13 UVLO/EN input Enable pin requiring 0.65V minimum for device enable with 0.55V typical threshold, 90mV hysteresis, and programmable under-voltage lockout via external resistor divider to AGND.
14 SYNC/DITHER/VH/CP bidirectional Multiplex pin functioning as external synchronous clock input (0.75×fRT to 1.5×fRT), spread spectrum dither capacitor pin (±6% to +5% modulation), VCC hold pin when >2.0V, and charge pump enable pin when >2.0V.
15 RT input Switching frequency programming pin regulated at 0.5V for 100kHz to 2.2MHz operation via external resistor with dynamic frequency programming during operation.
16 VREF/RANGE power_in 1.0V internal reference voltage output with 330pF to 1nF bypass capacitor requirement and VOUT range selection pin configured at startup with 75kΩ to 100kΩ (5V-20V) or 20kΩ to 35kΩ (15V-57V).
17 SS bidirectional Soft start capacitor pin charged by 20µA internal current source providing 120µs ramp with forced diode emulation below 1.5V and SS-FB clamp at 55mV above feedback voltage.
18 TRK input Output regulation target programming pin accepting 0.25V to 0.95V input voltage for dynamic output voltage control from external DAC or resistor divider to VREF.
19 AGND power_in Analog ground pin for low-level signal reference requiring connection to analog ground plane via short wide path.
20 COMP output Error amplifier output pin providing compensation network interface with 10MΩ output impedance and 3MHz bandwidth for loop filter design.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-20(3.5x3.5)
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: LM5123QRGRRQ1
  • Footprint: Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm
  • 3D model: VQFN-20(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: lm5123qrgrrq1-etched.step / lm5123qrgrrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5123qrgrrq1.step / lm5123qrgrrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 a525ddafaa5f90d0, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF