# LM5122MHE

**Texas Instruments** · DC-DC Converters · HTSSOP-20-EP

LM5122MHE from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNCOUT | output | Clock output pin providing a 180° shifted clock for interleaved operation, which can be left floating when unused. |
| 2 | OPT | input | Clock synchronization selection pin that also enables or disables SYNCOUT in master/slave configuration, and it should not be left floating. |
| 3 | CSN | input | Inverting input of the current sense amplifier, connected to the negative side of the current sense resistor. |
| 4 | CSP | input | Non-inverting input of the current sense amplifier, connected to the positive side of the current sense resistor. |
| 5 | VIN | power_in | Supply voltage input for the VCC regulator, rated 4.5 V to 65 V recommended operating range, connected with short low-impedance paths. |
| 6 | UVLO | input | Undervoltage lockout programming pin; below 0.4 V the regulator shuts down, and above 1.2 V the start-up sequence begins, and it should not be left floating. |
| 7 | SS | input | Soft-start programming pin where an external capacitor and an internal 10-µA current source set the error amplifier reference ramp rate. |
| 8 | SYNCIN/RT | input | Oscillator frequency is programmed by a single resistor to AGND, and the oscillator can be synchronized by a positive pulse applied to this pin, with a recommended maximum master oscillator frequency of 2 MHz. |
| 9 | AGND | power_in | Analog ground connection serving as the return for the internal voltage reference and analog circuits. |
| 10 | FB | input | Inverting input of the internal error amplifier where the regulation threshold is 1.2 V and the output voltage is set by a resistor divider. |
| 11 | COMP | output | Output of the internal error amplifier, where the loop compensation network connects between this pin and FB. |
| 12 | SLOPE | input | Slope compensation is programmed by a single resistor connected between SLOPE and AGND. |
| 13 | MODE | input | Switching mode selection pin with an internal 700-kΩ pullup and 100-kΩ pulldown defaulting to 0.15 V; voltages above the 1.2 V threshold enable forced PWM and below it enable diode emulation. |
| 14 | RES | output | Restart timer pin for an external capacitor that sets hiccup-mode off-time and restart delay, and it must connect directly to AGND when hiccup mode is not required. |
| 15 | PGND | power_in | Power ground connection for the low-side N-channel MOSFET gate driver, connected directly to the low-side MOSFET source. |
| 16 | LO | output | Low-side N-channel MOSFET gate drive output, connected to the low-side MOSFET gate through a short, low-inductance path. |
| 17 | VCC | power_in | VCC bias supply pin that must be locally decoupled to PGND with a low ESR/ESL capacitor placed as close to the controller as possible, with a recommended operating range of 14 V maximum. |
| 18 | SW | bidirectional | Switching node of the boost regulator, connected to the bootstrap capacitor, high-side MOSFET source and low-side MOSFET drain through short, low-inductance paths, rated up to 100 V. |
| 19 | HO | output | High-side N-channel MOSFET gate drive output, connected to the high-side MOSFET gate through a short, low-inductance path. |
| 20 | BST | power_in | High-side driver supply for bootstrap gate drive, connected to the bootstrap diode cathode and bootstrap capacitor, with a recommended BST to SW voltage of 3.8 V to 14 V. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN, CSP, CSN | -0.3 |  | 75 | V |  | 6 |
| BST to SW, FB, MODE, UVLO, OPT, VCC voltage | BST to SW, FB, MODE, UVLO, OPT, VCC | -0.3 |  | 15 | V |  | 6 |
| Switch node voltage | SW | -5 |  | 105 | V |  | 6 |
| BST voltage | BST | -0.3 |  | 115 | V |  | 6 |
| SS, SLOPE, SYNCIN/RT voltage | SS, SLOPE, SYNCIN/RT | -0.3 |  | 7 | V |  | 6 |
| CSP to CSN, PGND voltage | CSP to CSN, PGND | -0.3 |  | 0.3 | V |  | 6 |
| HO to SW voltage | HO to SW | -0.3 |  |  | V | maximum printed as BST to SW + 0.3 V | 6 |
| LO voltage | LO | -0.3 |  |  | V | maximum printed as VCC + 0.3 V | 6 |
| COMP, RES, SYNCOUT voltage | COMP, RES, SYNCOUT | -0.3 |  | 7 | V |  | 6 |
| Thermal junction temperature | TJ | -40 |  | 150 | °C |  | 6 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 6 |
| Input supply voltage | VIN | 4.5 |  | 65 | V |  | 7 |
| Low-side driver bias voltage | VCC |  |  | 14 | V |  | 7 |
| High-side driver bias voltage | BST to SW | 3.8 |  | 14 | V |  | 7 |
| Current sense common mode range | CSP, CSN | 3 |  | 65 | V |  | 7 |
| Switch node voltage | SW |  |  | 100 | V |  | 7 |
| Junction temperature | TJ | -40 |  | 125 | °C |  | 7 |
| VCC regulation | VCC(REG) | 6.9 | 7.6 | 8.3 | V | No load | 7 |
| VCC undervoltage threshold |  | 3.9 | 4 | 4.1 | V | VCC rising, VVIN = 4.5 V | 7 |
| UVLO threshold |  | 1.17 | 1.2 | 1.23 | V | UVLO rising | 7 |
| UVLO standby enable threshold |  | 0.3 | 0.4 | 0.5 | V | UVLO rising | 7 |
| UVLO hysteresis current |  | 7 | 10 | 13 | µA | VUVLO = 1.4 V | 7 |
| VIN shutdown current | ISHUTDOWN |  | 9 | 17 | µA | VUVLO = 0 V | 7 |
| VIN operating current (exclude the current into RT resistor) | IBIAS |  | 4 | 5 | mA | VUVLO = 2 V, non-switching | 7 |
| VCC sourcing current limit |  | 50 |  | 62 | mA | VVCC = 0 V | 7 |
| VCC dropout (VIN to VCC) |  |  | 0.28 | 0.5 | V | VVIN = 4.5 V, IVCC = 25 mA | 7 |
| VCC operating current (exclude the current into RT resistor) | IVCC |  | 3.5 | 5 | mA | VVCC = 8.3 V | 7 |
| VCC operating current (exclude the current into RT resistor) | IVCC |  | 4.5 | 8 | mA | VVCC = 12 V | 7 |
| Default MODE voltage |  | 145 | 155 | 170 | mV |  | 8 |
| Diode emulation mode threshold |  | 1.2 | 1.24 | 1.28 | V | MODE rising | 8 |
| FB reference voltage | VREF | 1.188 | 1.2 | 1.212 | V | Measured at FB, VFB = VCOMP | 8 |
| Slave mode threshold |  | 2.7 |  | 3.4 | V | FB rising | 8 |
| Switching frequency 1 | fSW1 | 400 | 450 | 500 | kHz | RT = 20 kΩ | 8 |
| Switching frequency 2 | fSW2 | 775 | 875 | 975 | kHz | RT = 10 kΩ | 8 |
| RT sync rising threshold |  | 2.5 |  | 2.9 | V | RT rising | 8 |
| RT sync falling threshold |  | 1.6 |  | 2 | V | RT falling | 8 |
| SYNCOUT high-state voltage |  | 3.3 |  | 4.3 | V | ISYNCOUT = -1 mA | 8 |
| Synchronization selection threshold |  | 2 | 3 | 4 | V | OPT rising | 8 |
| SLOPE output voltage |  | 1.17 | 1.2 | 1.23 | V |  | 8 |
| Slope compensation amplitude | VSLOPE | 1.375 | 1.65 | 1.925 | V | RSLOPE = 20 kΩ, fSW = 100 kHz, 50% duty cycle, TJ = -40°C to 125°C | 8 |
| Slope compensation amplitude | VSLOPE | 1.4 | 1.65 | 1.9 | V | RSLOPE = 20 kΩ, fSW = 100 kHz, 50% duty cycle, TJ = 25°C | 8 |
| SS current source | ISS-SOURCE | 7.5 | 10 | 12 | µA | VSS = 0 V | 8 |
| Forced LO off-time | tLO-OFF | 330 | 400 |  | ns | VVCC = 5.5 V | 8 |
| Forced LO off-time | tLO-OFF | 560 | 750 |  | ns | VVCC = 4.5 V | 8 |
| Cycle-by-cycle current limit threshold | VCS-TH1 | 65.5 | 75 | 87.5 | mV | CSP to CSN, TJ = -40°C to 125°C | 9 |
| Cycle-by-cycle current limit threshold | VCS-TH1 | 67 | 75 | 86 | mV | CSP to CSN, TJ = 25°C | 9 |
| Bias current matching | ICSP, ICSN | -1.75 | 1 | 3.75 | µA |  | 9 |
| RES restart threshold | VRES | 1.15 | 1.2 | 1.25 | V | RES rising | 9 |
| Fault-state RES charging current | IRES-SOURCE1 | 20 | 30 | 40 | µA |  | 9 |
| HO high-state voltage drop | VOHH |  | 0.15 | 0.24 | V | IHO = -100 mA, VOHH = VBST, VHO | 9 |
| LO fall to HO rise delay | tDLH | 50 | 80 | 115 | ns | No load, 50% to 50% | 10 |
| HO fall to LO rise delay | tDHL | 60 | 80 | 105 | ns | No load, 50% to 50% | 10 |
| Junction-to-ambient thermal resistance | RθJA |  | 36 |  | °C/W | PWP package, 20 pins | 7 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 20.1 |  | °C/W | PWP package, 20 pins | 7 |
| Junction-to-board thermal resistance | RθJB |  | 16.8 |  | °C/W | PWP package, 20 pins | 7 |
| Junction-to-top characterization parameter | ψJT |  | 0.4 |  | °C/W | PWP package, 20 pins | 7 |
| Junction-to-board characterization parameter | ψJB |  | 16.7 |  | °C/W | PWP package, 20 pins | 7 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 1.7 |  | °C/W | PWP package, 20 pins | 7 |

## CAD (KiCad official)

- Symbol: `LM5122MHE`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20-EP (KiCad packages3D, STEP)
- 3D model files: `lm5122mhe-etched.step` / `lm5122mhe-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm5122mhe.step` / `lm5122mhe.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/lm5122.pdf) (58 pp, sha256 `8b269c8857f1031c`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lm5122mhe-datasheet.pdf)