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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LM5119PSQE

Texas Instruments · DC-DC Converters · WQFN-32-EP(5x5)

LM5119PSQE from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC1	power_in	VCC bias pin for channel 1; the datasheet limits VCC to 5.5 V to 14 V recommended and -0.3 V to 15 V absolute maximum to AGND.
2	LO1	output	Low-side MOSFET gate drive output for the channel 1 synchronous MOSFET, routed through a short, low-inductance path; LO to AGND is limited to -0.3 V to VCC + 0.3 V.
3	PGND1	power_in	Power ground return for the channel 1 low-side gate driver, to be connected directly to the low side of the channel 1 current sense resistor.
4	CSG1	input	Kelvin ground connection to the channel 1 external current sense resistor, to be connected directly to the resistor's low side.
5	CS1	input	Current sense amplifier input for channel 1, connected to the high side of the channel 1 current sense resistor.
6	RAMP1	input	PWM ramp signal for channel 1; an external resistor and capacitor between SW1, RAMP1 and AGND set the ramp slope that emulates the buck inductor current.
7	SS1	input	Channel 1 error amplifier reference soft-start; an external capacitor with an internal 10-µA source sets the ramp rate, and the pin is held low when VCC1 or VCC2 is below 4.9 V, UVLO is below 1.25 V, or during thermal shutdown.
8	VCCDIS	input	Optional input that disables the internal VCC regulators when pulled above 1.25 V with an external bias supplied through a diode; a 500-kΩ internal pulldown enables the regulators when floating, and VCCDIS to AGND is limited to -0.3 V to 15 V.
9	FB1	input	Feedback and inverting input of the channel 1 error amplifier, with a regulation threshold of 0.8 V set by a resistor divider from the channel 1 output; FB1 to AGND is limited to -0.3 V to 15 V.
10	COMP1	output	Output of the channel 1 internal error amplifier, where the loop compensation network must be connected between this pin and FB1.
11	EN2	input	Channel 2 enable; a low level disables channel 2 while channel 1 and other functions stay active, and a 50-kΩ internal pullup enables channel 2 when the pin is floating; EN2 to AGND is limited to -0.3 V to 7 V.
12	AGND	power_in	Analog ground, the return for the internal 0.8-V voltage reference and analog circuits.
13	RT	input	Oscillator timing pin with a single resistor to AGND; the recommended maximum oscillator frequency is 1.5 MHz, corresponding to a 750-kHz maximum switching frequency per channel, and the oscillator can be synchronized by coupling a positive pulse through a small capacitor.
14	RES	output	Restart timer pin for an external capacitor that sets the hiccup-mode off time; hiccup begins after 256 consecutive cycle-by-cycle current-limited PWM cycles, and a 10-µA source charges the capacitor to the 1.25-V restart threshold.
15	COMP2	output	Output of the channel 2 internal error amplifier, where the loop compensation network must be connected between this pin and FB2.
16	FB2	input	Feedback and inverting input of the channel 2 error amplifier, with a regulation threshold of 0.8 V set by a resistor divider from the channel 2 output; FB2 to AGND is limited to -0.3 V to 15 V.
17	DEMB	input	Diode emulation enable input, where a low level latches the low-side MOSFET off for the rest of the PWM cycle when inductor current reverses, a high level disables diode emulation, and a 50-kΩ internal pulldown enables emulation when floating; DEMB to AGND is limited to -0.3 V to 15 V.
18	SS2	input	Channel 2 error amplifier reference soft-start; an external capacitor with an internal 10-µA source sets the ramp rate, and the pin is held low when VCC1 or VCC2 is below 4.9 V, UVLO is below 1.25 V, or during thermal shutdown.
19	RAMP2	input	PWM ramp signal for channel 2; an external resistor and capacitor between SW2, RAMP2 and AGND set the ramp slope that emulates the buck inductor current.
20	CS2	input	Current sense amplifier input for channel 2, connected to the high side of the channel 2 current sense resistor.
21	CSG2	input	Kelvin ground connection to the channel 2 external current sense resistor, to be connected directly to the resistor's low side.
22	PGND2	power_in	Power ground return for the channel 2 low-side gate driver, to be connected directly to the low side of the channel 2 current sense resistor.
23	LO2	output	Low-side MOSFET gate drive output for the channel 2 synchronous MOSFET, routed through a short, low-inductance path; LO to AGND is limited to -0.3 V to VCC + 0.3 V.
24	VCC2	power_in	VCC bias pin for channel 2; the datasheet limits VCC to 5.5 V to 14 V recommended and -0.3 V to 15 V absolute maximum to AGND.
25	SW2	bidirectional	Buck switching node for channel 2, connected to the channel 2 bootstrap capacitor, the high-side MOSFET source and the low-side MOSFET drain; SW2 to AGND is limited to -3 V to 75 V.
26	HO2	output	High-side MOSFET gate drive output for channel 2, routed through a short, low-inductance path to the high-side gate; HO to SW is limited to -0.3 V to HB + 0.3 V.
27	HB2	power_in	High-side bootstrap gate drive supply for channel 2, connected to the bootstrap diode cathode and bootstrap capacitor placed close to the controller; HB to SW is limited to 5.5 V to 14 V recommended and -0.3 V to 15 V absolute maximum.
28	UVLO	input	Undervoltage lockout programming pin: below 0.4 V the regulator shuts down, 0.4 V to 1.25 V gives standby with no switching, and above 1.25 V enables switching with a 20-µA hysteresis current source; UVLO to AGND is limited to -0.3 V to 15 V.
29	VIN	power_in	Supply voltage input for the VCC regulators; VIN is recommended at 5.5 V to 65 V, with a 75 V absolute maximum to AGND.
30	HB1	power_in	High-side bootstrap gate drive supply for channel 1, connected to the bootstrap diode cathode and bootstrap capacitor placed close to the controller; HB to SW is limited to 5.5 V to 14 V recommended and -0.3 V to 15 V absolute maximum.
31	HO1	output	High-side MOSFET gate drive output for channel 1, routed through a short, low-inductance path to the high-side gate; HO to SW is limited to -0.3 V to HB + 0.3 V.
32	SW1	bidirectional	Buck switching node for channel 1, connected to the channel 1 bootstrap capacitor, the high-side MOSFET source and the low-side MOSFET drain; SW1 to AGND is limited to -3 V to 75 V.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-32-EP(5x5)
Category	Power Management (PMIC)
Pins	33

CAD (KiCad official)

Symbol: LM5119PSQE
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: lm5119psqe-etched.step / lm5119psqe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5119psqe.step / lm5119psqe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (44 pp, sha256 bb3766da0f08d7d5, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF